MT40A512M8RH-083E Datasheet, PDF (196/365 Pages) Micron Technology – Programmable data strobe preambles

4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
READ Burst Operation
DDR4 READ commands support bursts of BL8 (fixed), BC4 (fixed), and BL8/BC4 on-
the-fly (OTF); OTF uses address A12 to control OTF when OTF is enabled:
• A12 = 0, BC4 (BC4 = burst chop)
• A12 = 1, BL8
READ commands can issue precharge automatically with a READ with auto precharge
command (RDA), and is enabled by A10 HIGH:
• READ command with A10 = 0 (RD) performs standard read, bank remains active after
READ burst.
• READ command with A10 = 1 (RDA) performs read with auto precharge, bank goes in
to precharge after READ burst.
Figure 127: READ Burst Operation, RL = 11 (AL = 0, CL = 11, BL8)
T0
CK_c
CK_t
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Ta9
Command READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Bank Group
Address
Address
BGa
Bank
col n
DQS_t
DQS_c
t_RPRE
t_RPST
DQ
CL = 11
RL = AL + CL
DO DO DO DO DO DO DO DO
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL8, RL = 0, AL = 0, CL = 11, Preamble = 1^tCK.
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
command at T0.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
196
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