MT40A512M8RH-083E Datasheet, PDF (35/365 Pages) Micron Technology – Programmable data strobe preambles

4Gb: x4, x8, x16 DDR4 SDRAM
RESET and Initialization Procedure
RESET and Initialization Procedure
To ensure proper device function, the power-up and reset initialization default values
for the following mode register (MR) settings are defined as:
• Gear-down mode (MR3 A[3]): 0 = 1/2 rate
• Per-DRAM addressability (MR3 A[4]): 0 = disable
• Maximum power-saving mode (MR4 A[1]): 0 = disable
• CS to command/address latency (MR4 A[8:6]): 000 = disable
• CA parity latency mode (MR5 A[2:0]): 000 = disable
• Hard Post Package Repair mode (MR4 A[13]) : 0 = Disable
• Soft Post Package Repair mode (MR4 A[5]) : 0 = Disable
Power-Up and Initialization Sequence
The following sequence is required for power-up and initialization:
1. Apply power (RESET_n and TEN should be maintained below 0.2 × V_DD while sup-
plies ramp up; all other inputs may be undefined). When supplies have ramped to
a valid stable level, RESET_n must be maintained below 0.2 × V_DD for a minimum
of ^tPW_RESET_L and TEN must be maintained below 0.2 × V_DD for a minimum of
700μs. CKE is pulled LOW anytime before RESET_n is de-asserted (minimum time
of 10ns). The power voltage ramp time between 300mV to V _DD,min must be no
greater than 200ms, and during the ramp, V_DD must be greater than or equal to
V_DDQ and (V_DD - V_DDQ) < 0.3V. V_PP must ramp at the same time or before V_DD, and
V_PP must be equal to or higher than V_DD at all times. After V_DD has ramped and
reached the stable level and after RESET_n goes high, the initialization sequence
must be started within 3 seconds. For debug purposes, the 3 second delay limit
may be extended to 60 minutes provided the DRAM is operated in this debug
mode for no more than 360 cumulative hours.
During power-up, the supply slew rate is governed by the limits stated in the table
below and either Condition A or Condition B must be met.
Table 5: Supply Power-up Slew Rate
Symbol
V_DD_SL, V_DDQ_SL,
V_PP_SL
V_DD_ona
V_DDQ_ona
Min
0.004
N/A
N/A
Max
600
200
200
Unit Comment
V/ms Measured between 300mV and 80% of
supply minimum
ms V_DD maximum ramp time from 300mV to
V_DD minimum
ms V_DDQ maximum ramp time from 300mV to
V_DDQ minimum
Note: 1. 20 MHz band-limited measurement.
• Condition A:
– Apply V_PP without any slope reversal before or at the same time as V_DD and
V_DDQ.
– V_DD and V_DDQ are driven from a single-power converter output and apply
V_DD/V_DDQ without any slope reversal before or at the same time as V_TT and
V_REFCA.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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