MT40A512M8RH-083E Datasheet, PDF (257/365 Pages) Micron Technology – Programmable data strobe preambles

4Gb: x4, x8, x16 DDR4 SDRAM
Dynamic ODT
Table 75: Dynamic ODT Latencies and Timing with Preamble Mode and CRC Mode Matrix
Symbol
ODTLcnw¹
ODTLcwn4
ODTLcwn8
1^tCK Parameter
CRC Off
CRC On
WL - 2
WL - 2
ODTLcnw + 4
ODTLcnw + 7
ODTLcnw + 6
ODTLcnw + 7
2^tCK Parameter
CRC Off
CRC On
WL - 3
WL - 3
ODTLcnw + 5
ODTLcnw + 8
ODTLcnw + 7
ODTLcnw + 8
Note: 1. ODTLcnw = WL - 2 (1^tCK preamble) or WL - 3 (2^tCK preamble).
Unit
t_CK
Figure 203: Dynamic ODT (1^t CK Preamble; CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled)
T0
T1
T2
T5
T6
T7
T8
T9
T10
T11
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
diff_CK
WR
Command
ODT
DODTLon = WL - 2
DODTLoff = WL - 2
t_{ADC (MAX)}
t_{ADC (MAX)}
t_{ADC (MAX)}
t_{ADC (MAX)}
R_TT
R_TT(Park)
R_TT(WR)
R_TT(Park)
R_TT(NOM)
R_TT(Park)
ODTLcnw
t_{ADC (MIN)}
ODTLcwn
t_{ADC (MIN)}
t_{ADC (MIN)}
t_{ADC (MIN)}
Transitioning
Notes: 1. ODTLcnw = WL - 2 (1^tCK preamble) or WL - 3 (2^tCK preamble).
2. If BC4, then ODTLcwn = WL + 4 if CRC disabled or WL + 5 if CRC enabled; If BL8, then
ODTLcwn = WL + 6 if CRC disabled or WL + 7 if CRC enabled.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
257
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