PIC32MX3XX_1 Datasheet, PDF (95/208 Pages) Microchip Technology – High-Performance, General Purpose and USB 32-bit Flash Microcontrollers

PIC32MX3XX/4XX
9.0 PREFETCH CACHE
Note 1: This data sheet summarizes the features
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Prefetch
Cache” (DS61119) of the “PIC32MX
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
Prefetch cache increases performance for applications
executing out of the cacheable program Flash memory
regions by implementing instruction caching, constant
data caching and instruction prefetching.
9.1 Features
• 16 Fully Associative Lockable Cache Lines
• 16-byte Cache Lines
• Up to four Cache Lines Allocated to Data
• Two Cache Lines with Address Mask to hold
repeated instructions
• Pseudo LRU replacement policy
• All Cache Lines are software writable
• 16-byte parallel memory fetch
• Predictive Instruction Prefetch
FIGURE 9-1:
PREFETCH MODULE BLOCK DIAGRAM
FSM
CTRL
Tag Logic
CTRL
Cache Line
Bus Control
Cache Control
Prefetch Control
Hit LRU
Miss LRU
Cache
Line
Address
Encode
RDATA
Hit Logic
Prefetch
CTRL
PFM
Prefetch
RDATA
© 2010 Microchip Technology Inc.
DS61143G-page 95