PIC32MX3XX_1 Datasheet, PDF (39/208 Pages) Microchip Technology – High-Performance, General Purpose and USB 32-bit Flash Microcontrollers

3.3 Power Management
The PIC32MX3XX/4XX Family core offers a number of
power management features, including low-power
design, active power management and power-down
modes of operation. The core is a static design that
supports slowing or halting the clocks, which reduces
system power consumption during idle periods.
3.3.1
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
The mechanism for invoking power-down mode is
through execution of the WAIT instruction. For more
information on power management, see Section 25.0
“Power-Saving Features”.
3.3.2 LOCAL CLOCK GATING
The majority of the power consumed by the
PIC32MX3XX/4XX Family core is in the clock tree and
clocking registers. The PIC32MX family uses extensive
use of local gated-clocks to reduce this dynamic power
consumption.
PIC32MX3XX/4XX
3.4 EJTAG Debug Support
The PIC32MX3XX/4XX Family core provides for an
Enhanced JTAG (EJTAG) interface for use in the
software debug of application and kernel code. In
addition to standard user mode and kernel modes of
operation, the PIC32MX3XX/4XX Family core provides
a Debug mode that is entered after a debug exception
(derived from a hardware breakpoint, single-step
exception, etc.) is taken and continues until a debug
exception return (DERET) instruction is executed.
During this time, the processor executes the debug
exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for
transferring test data in and out of the
PIC32MX3XX/4XX Family core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification define what
registers are selected and how they are used.
© 2010 Microchip Technology Inc.
DS61143G-page 39