PIC24FJ128GA010_09 Datasheet, PDF (94/240 Pages) Microchip Technology – 64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA010 FAMILY
7.1 CPU Clocking Scheme
The system clock source can be provided by one of
four sources:
• Primary Oscillator (POSC) on the OSC1 and
OSC2 pins
• Secondary Oscillator (SOSC) on the SOSCI and
SOSCO pins
• Fast Internal RC (FRC) Oscillator
• Low-Power Internal RC (LPRC) Oscillator
The primary oscillator and FRC sources have the
option of using the internal 4x PLL. The frequency of
the FRC clock source can optionally be reduced by the
programmable clock divider. The selected clock source
generates the processor and peripheral clock sources.
The processor clock source is divided by two to pro-
duce the internal instruction cycle clock, FCY. In this
document, the instruction cycle clock is also denoted
by FOSC/2. The internal instruction cycle clock, FOSC/2,
can be provided on the OSC2 I/O pin for some
operating modes of the primary oscillator.
7.2 Oscillator Configuration
The oscillator source (and operating mode) that is used
at a device Power-on Reset event is selected using Con-
figuration bit settings. The oscillator Configuration bit
settings are located in the Configuration registers in the
program memory (refer to Section 23.1 “Configura-
tion Bits” for further details.) The Primary Oscillator
Configuration
bits,
POSCMD1:POSCMD0
(Configuration Word 2<1:0>), and the Initial Oscillator
Select Configuration bits, FNOSC2:FNOSC0
(Configuration Word 2<10:8>), select the oscillator
source that is used at a Power-on Reset. The FRC
primary oscillator with postscaler (FRCDIV) is the
default (unprogrammed) selection. The secondary
oscillator, or one of the internal oscillators, may be
chosen by programming these bit locations.
The Configuration bits allow users to choose between
the various clock modes, shown in Table 7-1.
7.2.1
CLOCK SWITCHING MODE
CONFIGURATION BITS
The FCKSM Configuration bits (Configuration Word 2<7:6>)
are used to jointly configure device clock switching and
the Fail-Safe Clock Monitor (FSCM). Clock switching is
enabled only when FCKSM1 is programmed (‘0’). The
FSCM is enabled only when FCKSM1:FCKSM0 are
both programmed (‘00’).
TABLE 7-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator Source
POSCMD1:
POSCMD0
Fast RC Oscillator with Postscaler
Internal
11
(FRCDIV)
(Reserved)
Internal
xx
Low-Power RC Oscillator (LPRC)
Internal
11
Secondary (Timer1) Oscillator
Secondary
11
(SOSC)
Primary Oscillator (HS) with PLL
Primary
10
Module (HSPLL)
Primary Oscillator (XT) with PLL
Primary
01
Module (XTPLL)
Primary Oscillator (EC) with PLL
Primary
00
Module (ECPLL)
Primary Oscillator (HS)
Primary
10
Primary Oscillator (XT)
Primary
01
Primary Oscillator (EC)
Primary
00
Fast RC Oscillator with PLL Module
Internal
11
(FRCPLL)
Fast RC Oscillator (FRC)
Internal
11
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
FNOSC2:
FNOSC0
111
110
101
100
011
011
011
010
010
010
001
000
Note
1, 2
1
1
1
1
1
DS39747E-page 94
© 2009 Microchip Technology Inc.