PIC24FJ128GA010_09 Datasheet, PDF (115/240 Pages) Microchip Technology – 64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA010 FAMILY
13.0 OUTPUT COMPARE
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. Refer to Section 16. “Output
Compare” (DS39706) in the “PIC24F
Family Reference Manual” for more
information.
FIGURE 13-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
OCxRS⁽¹⁾
Set Flag bit
OCxIF⁽¹⁾
OCxR⁽¹⁾
Comparator
Output
Logic
3
OCM2:OCM0
Mode Select
SQ
R
OCx⁽¹⁾
Output Enable
OCFA or OCFB⁽²⁾
0
1
OCTSEL
0
1
16
16
TMR register inputs
from time bases
(see Note 3).
Period match signals
from time bases
(see Note 3).
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels, 1 through 5.
2: OCFA pin controls OC1-OC4 channels. OCFB pin controls OC5.
3: Each output compare channel can use either Timer2 or Timer3.
13.1 MODES OF OPERATION
Each output compare module has the following modes
of operation:
• Single Compare Match mode
• Dual Compare Match mode generating:
- Single Output Pulse mode
- Continuous Output Pulse mode
• Simple Pulse-Width Modulation mode:
- with Fault protection input
- without Fault protection input
13.2 Setup for Single Output Pulse
Generation
When the OCM control bits (OCxCON<2:0>) are set to
‘100’, the selected output compare channel initializes
the OCx pin to the low state and generates a single
output pulse.
© 2009 Microchip Technology Inc.
DS39747E-page 115