PIC24FJ128GA010_09 Datasheet, PDF (166/240 Pages) Microchip Technology – 64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA010 FAMILY
18.2 Calibration
The real-time crystal input can be calibrated using the
periodic auto-adjust feature. When properly calibrated,
the RTCC can provide an error of less than 3 seconds
per month. This is accomplished by finding the number
of error clock pulses and storing the value into the
lower half of the RCFGCAL register. The 8-bit signed
value loaded into the lower half of RCFGCAL is multi-
plied by four and will be either added or subtracted from
the RTCC timer, once every minute. Refer to the steps
below for RTCC calibration:
1. Using another timer resource on the device, the
user must find the error of the 32.768 kHz
crystal.
2. Once the error is known, it must be converted to
the number of error clock pulses per minute.
EQUATION 18-1:
(Ideal Frequency^† – Measured Frequency) * 60 = Clocks per Minute
† Ideal Frequency = 32,768 Hz
3. a) If the oscillator is faster then ideal (negative
result form step 2), the RCFGCAL register value
needs to be negative. This causes the specified
number of clock pulses to be subtracted from
the timer counter once every minute.
b) If the oscillator is slower then ideal (positive
result from step 2), the RCFGCAL register value
needs to be positive. This causes the specified
number of clock pulses to be subtracted from
the timer counter once every minute.
4. Divide the number of error clocks per minute by
4 to get the correct CAL value and load the
RCFGCAL register with the correct value. (Each
1-bit increment in CAL adds or subtracts
4 pulses). Load the RCFGCAL register with the
correct value.
Writes to the lower half of the RCFGCAL regis-
ter should only occur when the timer is turned
off, or immediately after the rising edge of the
seconds pulse.
Note:
It is up to the user to include in the error
value the initial error of the crystal, drift
due to temperature and drift due to crystal
aging.
18.3 Alarm
• Configurable from half second to one year
• Enabled using the ALRMEN bit
(ALCFGRPT<15>, Register 18-3)
• One-time alarm and repeat alarm options available
18.3.1 CONFIGURING THE ALARM
The alarm feature is enabled using the ALRMEN bit.
This bit is cleared when an alarm is issued. Writes to
ALRMVALH:ALRMVALL should only take place when
ALRMEN = 0.
As shown in Figure 18-2, the interval selection of the
alarm is configured through the AMASK bits
(ALCFGRPT<13:10>). These bits determine which and
how many digits of the alarm must match the clock
value for the alarm to occur. The alarm can also be con-
figured to repeat based on a preconfigured interval.
The amount of times this occurs once the alarm is
enabled is stored in the lower half of the ALCFGRPT
register.
When ALCFGRPT = 00 and the CHIME bit = 0
(ALCFGRPT<14>), the repeat function is disabled and
only a single alarm will occur. The alarm can be
repeated up to 255 times by loading the lower half of
the ALCFGRPT register with FFh.
After each alarm is issued, the ALCFGRPT register is
decremented by one. Once the register has reached
‘00’, the alarm will be issued one last time, after which,
the ALRMEN bit will be cleared automatically and the
alarm will turn off. Indefinite repetition of the alarm can
occur if the CHIME bit = 1. Instead of the alarm being
disabled when the ALCFGRPT register reaches ‘00’, it
will roll over to FF and continue counting indefinitely
when CHIME = 1.
18.3.2 ALARM INTERRUPT
At every alarm event an interrupt is generated. In addi-
tion, an alarm pulse output is provided that operates at
half the frequency of the alarm. This output is
completely synchronous to the RTCC clock and can be
used as a trigger clock to other peripherals.
Note:
Changing any of the registers, other then
the RCFGCAL and ALCFGRPT registers
and the CHIME bit while the alarm is
enabled (ALRMEN = 1), can result in a
false alarm event leading to a false alarm
interrupt. To avoid a false alarm event, the
timer and alarm values should only be
changed while the alarm is disabled
(ALRMEN = 0). It is recommended that the
ALCFGRPT register and CHIME bit be
changed when RTCSYNC = 0.
DS39747E-page 166
© 2009 Microchip Technology Inc.