PIC24FJ128GA010_09 Datasheet, PDF (122/240 Pages) Microchip Technology – 64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA010 FAMILY
To set up the SPI module for the Enhanced Buffer
Master mode of operation:
1. If using interrupts:
a) Clear the SPIxIF bit in the respective IFSx
register.
b) Set the SPIxIE bit in the respective IECx
register.
c) Write the SPIxIP bits in the respective IPCx
register.
2. Write the desired settings to the SPIxCON1 and
SPIxCON2 registers with MSTEN
(SPIxCON1<5>) = 1.
3. Clear the SPIROV bit (SPIxSTAT<6>).
4. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
5. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
6. Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
as soon as data is written to the SPIxBUF
register.
To set up the SPI module for the Enhanced Buffer
Slave mode of operation:
1. Clear the SPIxBUF register.
2. If using interrupts:
• Clear the SPIxIF bit in the respective IFSx
register.
• Set the SPIxIE bit in the respective IECx
register.
• Write the SPIxIP bits in the respective IPCx
register to set the interrupt priority.
3. Write the desired settings to the SPIxCON1 and
SPIxCON2 registers with MSTEN
(SPIxCON1<5>) = 0.
4. Clear the SMP bit.
5. If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SSx pin.
6. Clear the SPIROV bit (SPIxSTAT<6>).
7. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
8. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
FIGURE 14-1:
SPIx MODULE BLOCK DIAGRAM (STANDARD MODE)
SCKx
SSx/FSYNCx
Sync
Control
SDOx
Control
Clock
Select
Edge
Shift Control
SDIx
bit 0
SPIxSR
1:1 to 1:8
1:1/4/16/64
Secondary
Primary
FCY
Prescaler
Prescaler
SPIxCON1<1:0>
SPIxCON1<4:2>
Enable
Master Clock
Transfer
Transfer
SPIxBUF
Read SPIxBUF
Write SPIxBUF
16
Internal Data Bus
DS39747E-page 122
© 2009 Microchip Technology Inc.