PIC24FJ128GA010_09 Datasheet, PDF(40/240 Page) Microchip Technology – 64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers

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PIC24FJ128GA010_09 Datasheet, PDF (40/240 Pages) Microchip Technology – 64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers

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TABLE 3-24: PARALLEL MASTER/SLAVE PORT REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12

Bit 11 Bit 10 Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All

Resets

PMCON

0600 PMPEN

â

PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN CSF1 CSF0

ALP

CS2P CS1P

BEP

PMMODE

PMADDR(1)

PMDOUT1(1)

0602

0604

BUSY

CS2

IRQM1

CS1

IRQM0

INCM1

INCM0

MODE16 MODE1 MODE0 WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0

Parallel Port Destination Address<13:0> (Master modes)

Parallel Port Data Out Register 1 (Buffers 0 and 1)

PMDOUT2 0606

Parallel Port Data Out Register 2 (Buffers 2 and 3)

PMDIN1

0608

Parallel Port Data In Register 1 (Buffers 0 and 1)

PMDIN2

060A

Parallel Port Data In Register 2 (Buffers 2 and 3)

PMAEN

060C PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2

PMSTAT

060E IBF

IBOV

â

â

IB3F

IB2F

IB1F

IB0F

OBE OBUF

â

â

OB3E OB2E

Legend: â = unimplemented, read as â0â. Reset values are shown in hexadecimal.

Note 1: PMADDR and PMDOUT1 share the same physical register. The register functions as PMDOUT1 only in Slave modes, and as PMADDR only in Master modes.

WRSP

WAITE1

PTEN1

OB1E

RDSP

WAITE0

PTEN0

OB0E

0000

0000

0000

0000

0000

0000

0000

0000

008F

TABLE 3-25: REAL-TIME CLOCK AND CALENDAR REGISTER MAP

File Name Addr Bit 15 Bit 14

Bit 13

Bit 12 Bit 11 Bit 10

Bit 9

Bit 8

Bit 7 Bit 6 Bit 5 Bit 4

ALRMVAL

0620

Alarm Value Register Window Based on ALRMPTR<1:0>

ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5

RTCVAL

RCFGCAL(1)

0624

0626

RTCEN

RTCC Value Register Window Based on RTCPTR<1:0>

â RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5

Legend: x = unknown value on Reset, â = unimplemented, read as â0â. Reset values are shown in hexadecimal.

Note 1: RCFGCAL register Reset value dependent on type of Reset.

ARPT4

CAL4

Bit 3

ARPT3

CAL3

Bit 2

ARPT2

CAL2

Bit 1

ARPT1

CAL1

Bit 0

All

Resets

ARPT0

CAL0

xxxx

0000

xxxx

0000

TABLE 3-26: DUAL COMPARATOR REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

CMCON

CVRCON

Legend:

0630 CMIDL

â

C2EVT C1EVT C2EN C1EN C2OUTEN C1OUTEN

0632

â

â

â

â

â

â

â

â

â = unimplemented, read as â0â. Reset values are shown in hexadecimal.

C2OUT

CVREN

C1OUT

CVROE

Bit 5

C2INV

CVRR

Bit 4

Bit 3

C1INV C2NEG

CVRSS CVR3

Bit 2

C2POS

CVR2

Bit 1

C1NEG

CVR1

Bit 0

All

Resets

C1POS

CVR0

0000

0000

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