PIC24FJ128GA010_09 Datasheet, PDF (113/240 Pages) Microchip Technology – 64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA010 FAMILY
12.0 INPUT CAPTURE
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. Refer to Section 15. “Input Cap-
ture” (DS39701) in the “PIC24F Family
Reference Manual” for more information.
The input capture module has multiple operating
modes which are selected via the ICxCON register.
The operating modes include:
• Capture timer value on every falling edge of input
applied at the ICx pin
• Capture timer value on every rising edge of input
applied at the ICx pin
• Capture timer value on every fourth rising edge of
input applied at the ICx pin
• Capture timer value on every 16th rising edge of
input applied at the ICx pin
• Capture timer value on every rising and every
falling edge of input applied at the ICx pin
• Device wake-up from capture pin during CPU
Sleep and Idle modes
The input capture module has a four-level FIFO buffer.
The number of capture events required to generate a
CPU interrupt can be selected by the user.
FIGURE 12-1:
INPUT CAPTURE BLOCK DIAGRAM
From 16-Bit Timers
TMRy TMRx
ICx pin
Prescaler
Counter
(1, 4, 16)
Edge Detection Logic
and
Clock Synchronizer
3 ^{ICM<2:0> (ICxCON<2:0>)}
Mode Select
ICOV, ICBNE (ICxCON<4:3>)
ICI<1:0>
ICxCON
FIFO
R/W
Logic
Interrupt
Logic
16 16
10
ICTMR
(ICxCON<7>)
ICxBUF
System Bus
Set Flag ICxIF
(in IFSx Register)
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
© 2009 Microchip Technology Inc.
DS39747E-page 113