PIC16F636-I Datasheet, PDF (79/234 Pages) Microchip Technology – 8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC12F635/PIC16F636/639
7.5 Comparator Response Time
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the
comparator differs from the settling time of the voltage
reference. Therefore, both of these times must be
considered when determining the total response time
to a comparator input change. See the Comparator and
Voltage Specifications in Section 15.0 “Electrical
Specifications” for more details.
7.6 Comparator Interrupt Operation
The comparator interrupt flag is set whenever there is a
change in the output value of the comparator. Changes
are recognized by means of a mismatch circuit which
consists of two latches and an exclusive-or gate (see
Figures 7-8 and 7-9). One latch is updated with the
comparator output level when the CMCON0 register is
read. This latch retains the value until the next read of
the CMCON0 register or the occurrence of a Reset.
The other latch of the mismatch circuit is updated on
every Q1 system clock. A mismatch condition will occur
when a comparator output change is clocked through
the second latch on the Q1 clock cycle. The mismatch
condition will persist, holding the CxIF bit of the PIR1
register true, until either the CMCON0 register is read
or the comparator output returns to the previous state.
Note:
A write operation to the CMCON0 register
will also clear the mismatch condition
because all writes include a read
operation at the beginning of the write
cycle.
Software will need to maintain information about the
status of the comparator output to determine the actual
change that has occurred.
The CxIF bit of the PIR1 register, is the comparator
interrupt flag. This bit must be reset in software by
clearing it to ‘0’. Since it is also possible to write a ‘1’ to
this register, a simulated interrupt may be initiated.
The CxIE bit of the PIE1 register and the PEIE and GIE
bits of the INTCON register must all be set to enable
comparator interrupts. If any of these bits are cleared,
the interrupt is not enabled, although the CxIF bit of the
PIR1 register will still be set if an interrupt condition
occurs.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON0. This will end the
mismatch condition. See Figures 7-8 and 7-9.
b) Clear the CxIF interrupt flag.
A persistent mismatch condition will preclude clearing
the CxIF interrupt flag. Reading CMCON0 will end the
mismatch condition and allow the CxIF bit to be
cleared.
Note:
If a change in the CMCON0 register
(CxOUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CxIF interrupt flag may
not get set.
© 2007 Microchip Technology Inc.
DS41232D-page 77