PIC16F636-I Datasheet, PDF (129/234 Pages) Microchip Technology – 8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC12F635/PIC16F636/639
REGISTER 11-8: AFE STATUS REGISTER 7
R-0
CHZACT
bit 8
R-0
CHYACT
R-0
CHXACT
R-0
AGCACT
R-0
WAKEZ
R-0
WAKEY
R-0
WAKEX
R-0
ALARM
R-0
PEI
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 8
CHZACT: Channel Z Active⁽¹⁾ bit (cleared via Soft Reset)
1 = Channel Z is passing data after TAGC
0 = Channel Z is not passing data after TAGC
bit 7
CHYACT: Channel Y Active⁽¹⁾ bit (cleared via Soft Reset)
1 = Channel Y is passing data after TAGC
0 = Channel Y is not passing data after TAGC
bit 6
CHXACT: Channel X Active⁽¹⁾ bit (cleared via Soft Reset)
1 = Channel X is passing data after TAGC
0 = Channel X is not passing data after TAGC
bit 5
AGCACT: AGC Active Status bit (real time, cleared via Soft Reset)
1 = AGC is active (Input signal is strong). AGC is active when input signal level is approximately > 20 mVPP range.
0 = AGC is inactive (Input signal is weak)
bit 4
WAKEZ: Wake-up Channel Z Indicator Status bit (cleared via Soft Reset)
1 = Channel Z caused a AFE wake-up (passed ÷64 clock counter)
0 = Channel Z did not cause a AFE wake-up
bit 3
WAKEY: Wake-up Channel Y Indicator Status bit (cleared via Soft Reset)
1 = Channel Y caused a AFE wake-up (passed ÷64 clock counter)
0 = Channel Y did not cause a AFE wake-up
bit 2
WAKEX: Wake-up Channel X Indicator Status bit (cleared via Soft Reset)
1 = Channel X caused a AFE wake-up (passed ÷64 clock counter)
0 = Channel X did not cause a AFE wake-up
bit 1
ALARM: Indicates whether an Alarm timer time-out has occurred (cleared via read “Status Register command”)
1 = The Alarm timer time-out has occurred. It may cause the ALERT output to go low depending on the state of bit 4 of the
Configuration register 0
0 = The Alarm timer is not timed out
bit 0
PEI: Parity Error Indicator bit – indicates whether a Configuration register parity error has occurred (real time)
1 = A parity error has occurred and caused the ALERT output to go low
0 = A parity error has not occurred
Note 1: Bit is high whenever channel is passing data. Bit is low in Standby mode.
See Table 11-7 for the bit conditions of the AFE Status
Register after various SPI commands and the AFE
Power-on Reset.
TABLE 11-7: AFE STATUS REGISTER BIT CONDITION (AFTER POWER-ON RESET AND
VARIOUS SPI COMMANDS)
Condition
Bit 8
Bit 7
Bit 6
Bit 5
CHZACT CHYACT CHXACT AGCACT
Bit 4
WAKEZ
Bit 3
WAKEY
Bit 2
WAKEX
Bit 1
ALARM
Bit 0
PEI
POR
0
0
0
0
0
0
0
0
1
Read Command
u
u
u
u
u
u
u
0
u
(STATUS Register only)
Sleep Command
u
u
u
u
u
u
u
u
u
Soft Reset Executed⁽¹⁾
0
0
0
0
0
0
0
u
u
Legend:
Note 1:
u = unchanged
See Section 11.20 “Soft Reset” and Section 11.32.2.4 “Soft Reset Command” for the condition of Soft Reset
execution.
© 2007 Microchip Technology Inc.
DS41232D-page 127