PIC16F636-I Datasheet, PDF (122/234 Pages) Microchip Technology – 8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC12F635/PIC16F636/639
FIGURE 11-18: SPI READ SEQUENCE
2
CS
TCSSC
4 16 Clocks for Read Command,
Address and Dummy Data
THI TLO
SCLK/ALERT
ALERT
(output)
1
SCLK ^MSb
(input)
TSU THD
1/FSCLK
LFDATA/RSSI/
CCLK/SDIO
LFDATA SDI
3
(output) (input)
TCSH
6
7
TCSH
9
TSCCS TCS1
TCS0 TCSSC
10
8 16 Clocks for Read Result
TCSSC TCS1
TCS0
LSb
ALERT
SCLK
(output)
(input)
TDO
LFDATA
5 ^(output)
SDO
(output)
ALERT
(output)
LFDATA
(output)
MCU SPI Read Details:
1. Drive the AFE’s open collector ALERT output low.
• To ensure no false clocks occur when CS drops.
2. Drop CS
• AFE SCLK/ALERT becomes SCLK input.
• LFDATA/RSSI/CCLK/SDIO becomes SDI input.
3. Change LFDATA/RSSI/CCLK/SDIO connected pin to output.
• Driving SPI data.
4. Clock in 16-bit SPI Read sequence.
• Command, address and dummy data.
5. Change LFDATA/RSSI/CCLK/SDIO connected pin to input.
6. Raise CS to complete the SPI Read entry of command and address.
7. Drop CS.
• AFE SCLK/ALERT becomes SCLK input.
• LFDATA/RSSI/CCLK/SDIO becomes SDO output.
8. Clock out 16-bit SPI Read result.
• First seven bits clocked-out are dummy bits.
• Next eight bits are the Configuration register data.
• The last bit is the Configuration register row parity bit.
9. Raise CS to complete the SPI Read.
10. Change SCLK/ALERT back to input.
Note:
The TCSH is considered as one clock. Therefore, the
Configuration register data appears at 6th clock after TCSH.
DS41232D-page 120
© 2007 Microchip Technology Inc.