PIC16F636-I Datasheet, PDF (19/234 Pages) Microchip Technology – 8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC12F635/PIC16F636/639
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC12F635/PIC16F636/639 devices have a 13-bit
program counter capable of addressing an 8K x 14
program memory space. Only the first 1K x 14
(0000h-03FFh, for the PIC12F635) and 2K x 14
(0000h-07FFh, for the PIC16F636/639) is physically
implemented. Accessing a location above these
boundaries will cause a wraparound within the first
2K x 14 space. The Reset vector is at 0000h and the
interrupt vector is at 0004h (see Figure 2-1).
2.2 Data Memory Organization
The data memory (see Figure 2-2) is partitioned into
two banks, which contain the General Purpose
Registers (GPR) and the Special Function Registers
(SFR). The Special Function Registers are located in
the first 32 locations of each bank. Register locations
20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are GPRs,
implemented as static RAM for the PIC16F636/639.
For the PIC12F635, register locations 40h through 7Fh
are GPRs implemented as static RAM. Register
locations F0h-FFh in Bank 1 point to addresses
70h-7Fh in Bank 0. All other RAM is unimplemented
and returns ‘0’ when read. RP0 of the STATUS register
is the bank select bit.
RP1 RP0
0
0 → Bank 0 is selected
0
1 → Bank 1 is selected
1
0 → Bank 2 is selected
1
1 → Bank 3 is selected
FIGURE 2-1: PROGRAM MEMORY MAP AND
STACK OF THE PIC12F635
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 8
Reset Vector
0000h
Interrupt Vector
On-chip Program
Memory
Access 0-3FFh
0004h
0005h
03FFh
0400h
1FFFh
FIGURE 2-2: PROGRAM MEMORY MAP AND
STACK OF THE PIC16F636/639
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 8
Reset Vector
0000h
Interrupt Vector
On-chip Program
Memory
Access 0-7FFh
0004h
0005h
07FFh
0800h
1FFFh
© 2007 Microchip Technology Inc.
DS41232D-page 17