70353C Datasheet, PDF (60/76 Pages) Microchip Technology – Section 21. Enhanced Controller Area Network

dsPIC33E/PIC24E Family Reference Manual
21.9.2 Sample Point
The sample point is the point in a CAN bit time interval where the sample is taken and the bus
state is read and interpreted. It is situated between Phase Segment 1 and Phase Segment 2.
The CAN bus can be sampled once or three times at the sample point, as configured by the
Sample CAN bus Line bit (SAM) in ECAN Baud Rate Configuration register (CiCFG2<6>).
• If CiCFG2<6> = 1, the CAN bus is sampled three times at the sample point. The most
common of the three samples determines the bit value.
• If CiCFG2<6> = 0, the CAN bus is sampled only once at the sample point.
21.9.3 Synchronization
Two types of synchronization are used: Hard Synchronization and Resynchronization. A Hard
Synchronization occurs once at the SOF. Resynchronization occurs inside a frame.
• Hard synchronization – takes place on the recessive-to-dominant transition of the start
bit. The bit time is restarted from that edge.
• Resynchronization – takes place when a bit edge does not occur within the
Synchronization Segment in a message. One of the Phase Segments is shortened or
lengthened by an amount that depends on the phase error in the signal. The maximum
amount that can be used is determined by the Synchronization Jump Width parameter
(CiCFG1<7:6>).
The length of Phase Segment 1 and Phase Segment 2 can be changed depending on oscillator
tolerances of the transmitting and receiving node. Resynchronization compensates for any
phase shifts that may occur due to the different oscillators used by the transmitting and receiving
nodes.
• Bit Lengthening – If the transmitting node in ECAN has a slower oscillator than the
receiving node, the next falling edge, and therefore, the sample point can be delayed by
lengthening Phase Segment 1 in the bit time.
• Bit Shortening – If the transmitting node in ECAN has a faster oscillator than the receiving
node, the next falling edge, and therefore, the sample point of the next bit can be reduced
by shortening the Phase Segment 2 in the bit time.
• Synchronization Jump Width (SJW) – The SJW<1:0> bits (CiCFG1<7:6>) determine the
synchronization jump width by limiting the amount of lengthening or shortening that can be
applied to the Phase Segment 1 and Phase Segment 2 time intervals. This segment should
not be longer than Phase Segment 2 time. The width can be 1 TQ - 4 TQ.
21.9.4 ECAN Bit Time Calculations
The steps that must be performed by the user application to configure the bit timing for the ECAN
module are described below along with examples. It is assumed that the CANCKS bit
(CiCTRL<11>) is cleared resulting in FCAN = FP.
21.9.4.1 STEP 1: CALCULATE THE TIME QUANTUM FREQUENCY (FTQ)
• Select the Baud Rate (FBAUD) for the CAN Bus.
• Select the number of time quanta in a bit time, based on your system requirements.
Equation 21-2 shows the formula for computing FTQ.
Equation 21-2: Time Quantum Frequency (FTQ)
F_TQ = N × F_BAUD
Note 1: The total number of time quanta in a nominal bit time must be programmed
between 8 TQ and 25 TQ. Therefore, the FTQ is between 8 to 25 times the baud
rate (FBAUD).
2: Ensure that FTQ is an integer multiple of FBAUD to get the precise bit time.
Otherwise, the oscillator input frequency or the FBAUD may need to be changed.
DS70353C-page 21-60
© 2008-2011 Microchip Technology Inc.