70353C Datasheet, PDF (10/76 Pages) Microchip Technology – Section 21. Enhanced Controller Area Network

dsPIC33E/PIC24E Family Reference Manual
21.3.4 ECAN FIFO Control/Status Registers
• CiFCTRL: ECAN FIFO Control Register
This register controls operation of the receive buffer FIFO. It specifies the FIFO start address
and the number of message buffers reserved for ECAN in the device RAM (see
Register 21-18). This register is only accessible by the user application when the WIN bit is
cleared (CiCTRL1<0> = 0).
• CiFIFO: ECAN FIFO Status Register
This register contains write and read pointers. The write pointer indicates which buffer
contains the most-recently received data. The read pointer tells the user application which
buffer to read next (see Register 21-19). This register is only accessible by the user
application when the WIN bit is cleared (CiCTRL1<0> = 0).
21.3.5 ECAN Interrupt Control/Status Registers
• CiINTF: ECAN Interrupt Flag Register
This register provides the status of various interrupt sources in the ECAN module (see
Register 21-20). This register is only accessible by the user application when the WIN bit is
cleared (CiCTRL1<0> = 0).
• CiINTE: ECAN Interrupt Enable Register⁽¹⁾
This register is used to selectively enable/disable the seven main sources of interrupt:
transmit buffer interrupt, receive buffer interrupt, receive buffer overflow interrupt, FIFO
almost full interrupt, error interrupt, wake-up interrupt, and invalid message received
interrupt (see Register 21-21). This register is only accessible by the user application when
the WIN bit is cleared (CiCTRL1<0> = 0).
• CiVEC: ECAN Interrupt Code Register
This register provides interrupt code bits that can be used with a jump table for efficient
handling of interrupts (see Register 21-22). This register is only accessible by the user
application when the WIN bit is cleared (CiCTRL1<0> = 0).
21.3.6 ECAN Control and Error Counter Registers
• CiCTRL1: ECAN Control Register 1
This register sets the ECAN module operation modes (see Register 21-23). This register is
only accessible by the user application when the WIN bit is cleared (CiCTRL1<0> = 0).
• CiCTRL2: ECAN Control Register 2
This register contains the DeviceNet™ filtering control bits (see Register 21-24).
• CiTRmnCON: ECAN TX/RX Buffer m Control Register (m = 0,2,4,6; n = 1,3,5,7)
These registers configure and control the message buffers (see Register 21-25).
• CiEC: ECAN Transmit/Receive Error Count Register
This register counts the transmit and receive errors. The user application can read this
register to determine the current number of transmit and receive
errors (see Register 21-26).
• CiRXD: ECAN Receive Data Register
This register temporarily holds every received word. This is the register from which the DMA
controller reads data into the DMA buffer.
• CiTXD: ECAN Transmit Data Register
This register temporarily holds every transmission. This is the register to which the DMA
Controller writes data from the DMA buffer.
DS70353C-page 21-10
© 2008-2011 Microchip Technology Inc.