70353C Datasheet, PDF (50/76 Pages) Microchip Technology – Section 21. Enhanced Controller Area Network

dsPIC33E/PIC24E Family Reference Manual
21.7.2 Buffer Selection and DMA Transfer
As illustrated in Figure 21-13, if a filter match occurs, a DMA transfer request is generated by the
ECAN module to the DMA Controller to automatically copy the received message into the
appropriate message buffer in a user-defined device RAM area. The ECAN module supports up
to 32 message buffers. The user application can use the DMA Buffer Size bits (DMABS<2:0>) in
the ECAN FIFO Control register (CiFCTRL<15:13>) to select either 4, 6, 8, 12, 16, 24 or 32
message buffers. The selection of the receive buffer index (and therefore the device RAM
addresses in which a message is written by the DMA Controller) is dependent on which filter
matched the incoming identifier, and is configurable by the user application. The DMA Controller
moves the data into the appropriate addresses in the device RAM area and generates a DMA
interrupt after the user-specified number of words are transferred. For more details on DMA
channel configuration for ECAN data transfers, refer to 21.8 “DMA Controller Configuration”.
Figure 21-13: Buffer Selection and DMA Transfer
ECAN™ Buffers in Device RAM
Message Buffer 0
Message Buffer 1
Start of ECAN Buffers
Message Buffer 7
+ _{Message stored here}
Word 0
Word 1
Message
Word 2
Assembly
Word 3
Buffer
Word 4
Word 5
DMA
Transfer
x16
Word 6
Word 7
Message Buffer 31
User-Defined
Acceptance
Filters
(0-15)
Identifier
Comparison
Filter 0
Filter 1
Filter 2
Filter 3
Filter 4
Filter 5
Filter 6
Filter 7
Filter 8
Filter 9
Filter 10
Filter 11
Filter 12
Filter 13
Filter 14
Filter 15
Filter Buffer Pointers (0-15)
Filter Match
F0BP<3:0>
F1BP<3:0>
F2BP<3:0>
F3BP<3:0>
F4BP<3:0>
F5BP<3:0>
F6BP<3:0>
F7BP<3:0>
F8BP<3:0>
F9BP<3:0>
F10BP<3:0>
F11BP<3:0>
F12BP<3:0>
F13BP<3:0>
F14BP<3:0>
F15BP<3:0>
F1BP<3:0> = 0111
DS70353C-page 21-50
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