70353C Datasheet, PDF (24/76 Pages) Microchip Technology – Section 21. Enhanced Controller Area Network

dsPIC33E/PIC24E Family Reference Manual
Register 21-22: CiVEC: ECAN Interrupt Code Register
U-0
—
bit 15
U-0
U-0
R-0
R-0
—
—
R-0
R-0
FILHIT<4:0>
R-0
bit 8
U-0
—
bit 7
R-1
R-0
R-0
R-0
R-0
ICODE<6:0>^(1,2)
R-0
R-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
bit 7
bit 6-0
Unimplemented: Read as ‘0’
FILHIT<4:0>: Filter Hit Number bits
10000-11111 = Reserved; do not use
01111 = Filter 15
•
•
•
00001 = Filter 1
00000 = Filter 0
Unimplemented: Read as ‘0’
ICODE<6:0>: Interrupt Flag Code bits^(1,2)
1000101-1111111 = Reserved; do not use
1000100 = FIFO almost full interrupt
1000011 = Receiver overflow interrupt
1000010 = Wake-up interrupt
1000001 = Error interrupt
1000000 = No interrupt
0100000-0111111 = Reserved; do not use
0011111 = RB31 buffer Interrupt
0011110 = RB30 buffer Interrupt
•
•
•
0001001 = RB9 buffer interrupt
0001000 = RB8 buffer interrupt
0000111 = TRB7 buffer interrupt
0000110 = TRB6 buffer interrupt
0000101 = TRB5 buffer interrupt
0000100 = TRB4 buffer interrupt
0000011 = TRB3 buffer interrupt
0000010 = TRB2 buffer interrupt
0000001 = TRB1 buffer interrupt
0000000 = TRB0 Buffer interrupt
Note 1:
2:
The ICODE<6:0> bits are cleared when the corresponding interrupts flag bits in the CiINTF register are
cleared.
The ICODE<6:0> bits only reflect the status of enabled interrupt sources. The corresponding bits in the
CiINTE register must be set.
DS70353C-page 21-24
© 2008-2011 Microchip Technology Inc.