70353C Datasheet, PDF (3/76 Pages) Microchip Technology – Section 21. Enhanced Controller Area Network

Section 21. Enhanced Controller Area Network (ECAN™)
Figure 21-2 illustrates the general structure of the ECAN module and its interaction with the DMA
Controller and device RAM.
Figure 21-2: ECAN™ Interaction with DMA
CiTX
CiRX
ECAN™ Module
CAN
Protocol
Engine
ECAN
Transmit
Register
(CiTXD)
Acceptance
Filter 0-15
ECAN
Receive
Register
(CiRXD)
TX DMA
Interface
TX
Request
DMA
Channel
RX DMA
Interface
RX
Request _DMA
Channel
Message Buffer
(Device RAM)
Message Buffer 0
Message Buffer 1
Message Buffer 7
Message Buffer 8
Message Buffer 31
21
21.1.1 ECAN Module
The ECAN module consists of a protocol engine, message acceptance filters, and separate
transmit and receive DMA interfaces. The protocol engine transmits and receives messages to
and from the CAN bus (as per the CAN Specification 2.0B protocol). The user-configurable
acceptance filters are used by the ECAN module to examine the received message and
determine if it should be stored in the DMA message buffer or discarded.
For received messages, the receive DMA interface generates a receive data interrupt to initiate
a DMA cycle. The receive DMA channel reads data from the CiRXD register and writes it into the
message buffer.
For transmit messages, the transmit DMA interface generates a transmit data interrupt to start a
DMA cycle. The transmit DMA channel reads from the message buffer and writes to the CiTXD
register for message transmission.
21.1.2 Message Buffers
The ECAN module supports up to 32 message buffers for storing data transmitted or received on
the CAN bus. These buffers can be located anywhere in device RAM (start address of the buffer
may be needed to be aligned on an address boundary). Message buffers 0-7 can be configured
for either transmit or receive operation. Message buffers 8-31 are receive-only buffers and
cannot be used for message transmission.
21.1.3 DMA Controller
The DMA controller acts as an interface between the message buffers and ECAN to transfer data
back and forth without CPU intervention. The DMA controller supports up to 15 channels for
transferring data between the device RAM and the dsPIC33E/PIC24E device peripherals. Two
separate DMA channels are required to support the CAN message transmission and the CAN
message reception.
Each DMA channel has a DMA Request register (DMAxREQ), which is used by the user
application to assign an interrupt event to trigger a DMA-based message transfer.
© 2008-2011 Microchip Technology Inc.
DS70353C-page 21-3