70353C Datasheet, PDF (52/76 Pages) Microchip Technology – Section 21. Enhanced Controller Area Network

dsPIC33E/PIC24E Family Reference Manual
21.7.2.5 RECEIVE BUFFER STATUS BITS
The receive buffers contain two status bits per message buffer, the Message Buffer Full
Flag (RXFULn), and the Message Buffer Overflow Flag (RXOVFn). These status bits are
grouped into registers for buffer-full status and buffer-overflow status.
• CiRXFUL1: ECAN Receive Buffer Full Register 1
• CiRXFUL2: ECAN Receive Buffer Full Register 2
• CiRXOVF1: ECAN Receive Buffer Overflow Register 1
• CiRXOVF2: ECAN Receive Buffer Overflow Register 2
When a received message is stored into a message buffer, the respective Buffer Full Flag
(RXFULn) is set in the Receive Buffer Full register, and a received buffer interrupt (CiINTF<1>)
is generated. If an incoming message caused a filter match, and the message buffer assigned to
the matching filter is full (that is, the RXFULn bit associated with that buffer is already ‘1’), the
corresponding RXOVFn bit (where ‘n’ is the number of the message buffer associated with that
buffer) is set and a received buffer overflow interrupt is generated (CiINTF<2>). The message is
lost.
Note:
If multiple filters match the identifier of the incoming message, and all the message
buffers assigned to all the matching filters are full, the RXOVFn bit corresponding
to the lowest numbered matching filter is set.
21.7.3 FIFO Buffer Operation
The ECAN module supports up to 32 message buffers. The user application can employ the DMA
Buffer Size bits (DMABS<2:0>) in the ECAN FIFO Control register (CiFCTRL<15:13>) to specify
the 4, 6, 8, 12, 16, 24 or 32 message buffers. The FIFO Start Area (FSA<4:0>)
bits (CiFCTRL<4:0>) are used to specify the start of the FIFO within the buffer area. The end of
FIFO is based on the number of message buffers defined in the DMABS<2:0> bits.
The user application should not allocate a FIFO area that contains the transmit buffers. Should
this condition occur, the module will attempt to point to the transmit buffer, but when a message
is received for that buffer, an overflow condition will cause the message contents to be lost.
Figure 21-14 illustrates that one of the message acceptance filters is set to store a received
message in FIFO (FnBP = 1111). The start of FIFO is set to message buffer 5
(CiFCTRL<4:0> = 00101) and the end of FIFO is set to message buffer 11
(CiFCTRL<15:13> = 011) by allocating 12 message buffers.
Figure 21-14: Receiving Messages in FIFO
Filter Masks
MASK 2
MASK 1
MASK 0
Message Acceptance Filters
Filter 15
Filter 0
1
FnBP
Device RAM
Message Buffer 0
Message Buffer 1
Message Buffer 5
2
FIFO Start
FIFO
FIFO Buffer 0
FIFO Buffer 1
Message Buffer 11
FIFO End
3
Message Buffer 31
FIFO Buffer n
Note 1:
2:
3:
The Acceptance Filter Buffer Pointer (FnBP) should be ‘1111’ to store the received message in FIFO.
The starting address of the FIFO is specified by the FSA<4:0> bits (CiFCTRL<4:0>). In the figure, FSA <4:0> = 00101.
The end address of the FIFO is specified by DMABS<2:0> = 011 (CiFCTRL<15:13>).
DS70353C-page 21-52
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