70353C Datasheet, PDF (23/76 Pages) Microchip Technology – Section 21. Enhanced Controller Area Network

Section 21. Enhanced Controller Area Network (ECAN™)
Register 21-21: CiINTE: ECAN Interrupt Enable Register⁽¹⁾
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
IVRIE
bit 7
R/W-0
WAKIE
R/W-0
ERRIE
R/W-0
—
R/W-0
FIFOIE
R/W-0
RBOVIE
R/W-0
RBIE
R/W-0
TBIE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
IVRIE: Invalid Message Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
WAKIE: Bus Wake-up Activity Interrupt Flag bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
ERRIE: Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
FIFOIE: FIFO Almost Full Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
RBOVIE: RX Buffer Overflow Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
RBIE: RX Buffer Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
TBIE: TX Buffer Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Note 1: Setting a bit in the CiINTE register only enables the corresponding interrupt source. To generate a
Ci interrupt, the CiIE bit must be set in the Interrupt module.
21
© 2008-2011 Microchip Technology Inc.
DS70353C-page 21-23