70353C Datasheet, PDF (20/76 Pages) Microchip Technology – Section 21. Enhanced Controller Area Network

dsPIC33E/PIC24E Family Reference Manual
Register 21-18: CiFCTRL: ECAN FIFO Control Register
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
DMABS<2:0>
—
—
—
—
—
bit 15
bit 8
U-0
—
bit 7
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
FSA<4:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-5
bit 4-0
DMABS<2:0>: Message Buffer Size bits
111 = Reserved; do not use
110 = 32 buffers in device RAM
101 = 24 buffers in device RAM
100 = 16 buffers in device RAM
011 = 12 buffers in device RAM
010 = Eight buffers in device RAM
001 = Six buffers in device RAM
000 = Four buffers in device RAM
Unimplemented: Read as ‘0’
FSA<4:0>: FIFO Start Area bits
11111 = Read buffer RB31
11110 = Read buffer RB30
•
•
•
00010 = TX/RX buffer TRB2
00001 = TX/RX buffer TRB1
00000 = TX/RX buffer TRB0
DS70353C-page 21-20
© 2008-2011 Microchip Technology Inc.