70353C Datasheet, PDF (53/76 Pages) Microchip Technology – Section 21. Enhanced Controller Area Network

Section 21. Enhanced Controller Area Network (ECAN™)
21.7.3.1 RECEIVING MESSAGES INTO FIFO AREA
The acceptance filter stores the received message in the FIFO area when FnBP<3:0> = 1111.
It uses a simple buffer pointer, beginning with the start of the FIFO as defined above, and
incrementing sequentially through the set of buffers within the FIFO area. When the end of the
buffer is reached, the counter wraps and points to the start of the FIFO area.
The write pointer value is accessible and is readable only by the user software in the FBP<5:0>
bits (CiFIFO<13:8>). When the message is stored in the buffer, the RXFUL bit associated with
the buffer is set, and the FIFO buffer counter increments.
If the FBP<5:0> value points to a buffer, and the RXFUL bit associated with that buffer is
already ‘1’ at the time of the filter hit and before writing of the message contents, the RXOVL bit
associated with that buffer is set and the message is lost. After the message is lost, the FBP<5:0>
value increments normally.
If the FBP<5:0> value points to a transmit/receive buffer that is selected as a transmit buffer at
the time of the filter hit and before writing of the message contents, the RXOVL bit associated
with that buffer is set and the message is lost. After the message is lost, the FBP<5:0> value
increments normally.
The user software unloads the FIFO by reading the contents of a buffer. Once the buffer location
is read, the user software clears the RXFUL bit corresponding to that buffer. When an RXFUL bit
is cleared, the number of that corresponding buffer, plus one, is written to the FNRB<5:0> bits
(CiFIFO<5:0>) by the module. Only the user software can read this value; left shift it by four bits
and use it as an address offset for the next buffer to be read. The user software should read the
buffers sequentially.
The module generates an interrupt condition, if the FIFO is about to be full. This condition is
computed as shown in Equation 21-1.
Equation 21-1: FIFO Interrupt Calculation
FNRB – FBP = 1
Or
(FNRB = START) and (FBP = END)
The interrupt is generated as the RXFUL bit is set for the buffer that was just written to, and after
the FBP bit has been updated. The computation uses the updated FBP value.
21.7.4 FIFO Example
Figure 21-15 illustrates seven case examples of FIFO operation. The cases illustrated assume
that the Start of FIFO is set to message buffer 5 (CiFCTRL<4:0> = 101) and the End of FIFO is
set to message buffer 11 (CiFCTRL<15:13> = 011).
• Case 1 – is the initialized case of the FIFO before any messages are received. The FIFO
Buffer Pointer points to message buffer 5 (FRB = 5), and the FIFO Next Read Buffer
Pointer points to message buffer 6 (FNRB = 5).
• Case 2 – shows the FIFO after one message is received and transferred to message
buffer 5. The FIFO Buffer Pointer is incremented (FBP = 6), and the RXFUL status bit for
message buffer 5 is set (RXFUL = 1).
• Case 3 – shows the FIFO after the sixth received message. The FIFO Buffer Pointer points
to the last location in the FIFO area (FBP = 5 + 6 = 11), and the FIFO Next Read Pointer
points to start of the FIFO (FNRB = 5). In this case, the FIFO is almost full and generates a
FIFO interrupt.
• Case 4 – shows the FIFO after the user software reads the first received message. When the
user software clears the RXFUL status bit for message buffer 5, the module writes the FIFO
Next Read Buffer Pointer with message buffer 5 plus 1 (FNRB = 5 + 1 = 6).
• Case 5 – shows the FIFO after the seventh message is received and written to message
buffer 11. The RXFUL status bit for message buffer 11 is set (RXFUL = 1). Instead of
incrementing, the FIFO Buffer Pointer is reloaded with the FIFO Start address
(FBP = FSA = 5). Note that FBP is now mathematically one less than FNRB, which is the
condition that generates the FIFO interrupt at the time the RXFUL status bit is set for
message buffer 11.
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DS70353C-page 21-53