DSPIC33FJ32GS406_12 Datasheet, PDF (241/456 Pages) Microchip Technology – 16-Bit Digital Signal Controllers with High-Speed PWM, ADC and Comparators

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-11: PWMCONx: PWM CONTROL x REGISTER
HS/HC-0
FLTSTAT⁽¹⁾
bit 15
HS/HC-0
CLSTAT⁽¹⁾
HS/HC-0
TRGSTAT
R/W-0
FLTIEN
R/W-0
CLIEN
R/W-0
TRGIEN
R/W-0
ITB⁽³⁾
R/W-0
MDCS⁽³⁾
bit 8
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
DTC<1:0>
DTCP⁽⁴⁾
—
MTBS
CAM^(2,3,5) XPRES⁽⁶⁾
IUE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
FLTSTAT: Fault Interrupt Status bit⁽¹⁾
1 = Fault interrupt is pending
0 = No Fault interrupt is pending
This bit is cleared by setting FLTIEN = 0.
CLSTAT: Current-Limit Interrupt Status bit⁽¹⁾
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending
This bit is cleared by setting CLIEN = 0.
TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = No trigger interrupt is pending
This bit is cleared by setting TRGIEN = 0.
FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled
0 = Fault interrupt is disabled and FLTSTAT bit is cleared
CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt is enabled
0 = Current-limit interrupt is disabled and CLSTAT bit is cleared
TRGIEN: Trigger Interrupt Enable bit
1 = A trigger event generates an interrupt request
0 = Trigger event interrupts are disabled and TRGSTAT bit is cleared
ITB: Independent Time Base Mode bit⁽³⁾
1 = PHASEx/SPHASEx registers provide time base period for this PWM generator
0 = PTPER register provides timing for this PWM generator
MDCS: Master Duty Cycle Register Select bit⁽³⁾
1 = MDC register provides duty cycle information for this PWM generator
0 = PDCx and SDCx registers provide duty cycle information for this PWM generator
Note 1:
2:
3:
4:
5:
6:
Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
These bits should not be changed after the PWM is enabled by setting PTEN (PTCON<15>) = 1.
For DTCP to be effective, DTC<1:0> must be set to ‘11’; otherwise, DTCP is ignored.
Center-Aligned mode ignores the Least Significant 3 bits of the Duty Cycle, Phase and Dead-Time
registers. The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to
the fastest clock.
Configure CLMOD (FCLCONX<8>) = 0 and ITB (PWMCONx<9>) = 1 to operate in External Period
Reset mode.
 2009-2012 Microchip Technology Inc.
DS70591E-page 241