DSPIC33FJ32GS406_12 Datasheet, PDF (237/456 Pages) Microchip Technology – 16-Bit Digital Signal Controllers with High-Speed PWM, ADC and Comparators

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-5: STCON: PWM SECONDARY MASTER TIME BASE CONTROL REGISTER
U-0
U-0
U-0
HS/HC-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
SESTAT
SEIEN
EIPU⁽¹⁾
SYNCPOL SYNCOEN
bit 15
bit 8
R/W-0
SYNCEN
bit 7
R/W-0
R/W-0
R/W-0
SYNCSRC<2:0>
R/W-0
R/W-0
R/W-0
SEVTPS<3:0>
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6-4
bit 3-0
Unimplemented: Read as ‘0’
SESTAT: Special Event Interrupt Status bit
1 = Secondary Special Event Interrupt is pending
0 = Secondary Special Event Interrupt is not pending
SEIEN: Special Event Interrupt Enable bit
1 = Secondary Special Event Interrupt is enabled
0 = Secondary Special Event Interrupt is disabled
EIPU: Enable Immediate Period Updates bit⁽¹⁾
1 = Active Secondary Period register is updated immediately
0 = Active Secondary Period register updates occur on PWM cycle boundaries
SYNCPOL: Synchronize Input and Output Polarity bit
1 = SYNCIx/SYNCO2 polarity is inverted (active-low)
0 = SYNCIx/SYNCO2 polarity is active-high
SYNCOEN: Secondary Master Time Base Synchronization Enable bit
1 = SYNCO2 output is enabled.
0 = SYNCO2 output is disabled
SYNCEN: External Secondary Master Time Base Synchronization Enable bit
1 = External synchronization of secondary time base is enabled
0 = External synchronization of secondary time base is disabled
SYNCSRC<2:0>: PWM Secondary Time Base Synchronization Source Selection bits
111 = Reserved
101 = Reserved
100 = Reserved
011 = SYNCI4
010 = SYNCI3
001 = SYNCI2
000 = SYNCI1
SEVTPS<3:0>: PWM Secondary Special Event Trigger Output Postscaler Select bits
1111 = 1:16 Postcale
0001 = 1:2 Postcale
•
•
•
0000 = 1:1 Postscale
Note 1: This bit only applies to the secondary master time base period.
 2009-2012 Microchip Technology Inc.
DS70591E-page 237