DSPIC33FJ32GS406_12 Datasheet, PDF (21/456 Pages) Microchip Technology – 16-Bit Digital Signal Controllers with High-Speed PWM, ADC and Comparators

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
Type
Description
FLT1-FLT23
SYNCI1-SYNCI4
SYNCO1-SYNCO2
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
PWM5L
PWM5H
PWM6L
PWM6H
PWM7L
PWM7H
PWM8L
PWM8H
PWM9L
PWM9H
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I
ST Fault inputs to PWM module.
I
ST External synchronization signal to PWM master time base.
O
— PWM master time base for external device synchronization.
O
— PWM1 low output.
O
— PWM1 high output.
O
— PWM2 low output.
O
— PWM2 high output.
O
— PWM3 low output.
O
— PWM3 high output.
O
— PWM4 low output.
O
— PWM4 high output.
O
— PWM5 low output.
O
— PWM5 high output.
O
— PWM6 low output.
O
— PWM6 high output.
O
— PWM7 low output.
O
— PWM7 high output.
O
— PWM8 low output.
O
— PWM8 high output.
O
— PWM9 low output.
O
— PWM9 high output.
I/O
ST Data I/O pin for Programming/Debugging Communication Channel 1.
I
ST Clock input pin for Programming/Debugging Communication Channel 1.
I/O
ST Data I/O pin for Programming/Debugging Communication Channel 2.
I
ST Clock input pin for Programming/Debugging Communication Channel 2.
I/O
ST Data I/O pin for Programming/Debugging Communication Channel 3.
I
ST Clock input pin for Programming/Debugging Communication Channel 3.
MCLR
AVDD
AVSS
VDD
VCAP
VSS
Legend:
I/P
ST Master Clear (Reset) input. This pin is an active-low Reset to the
device.
P
P Positive supply for analog modules.
P
P Ground reference for analog modules.
P
— Positive supply for peripheral logic and I/O pins.
P
— CPU logic filter capacitor connection.
P
— Ground reference for logic and I/O pins.
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-Transistor Logic
Analog = Analog input
P = Power
I = Input
O = Output
 2009-2012 Microchip Technology Inc.
DS70591E-page 21