DSPIC33FJ32GS406_12 Datasheet, PDF (120/456 Pages) Microchip Technology – 16-Bit Digital Signal Controllers with High-Speed PWM, ADC and Comparators

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
6.4 External Reset (EXTR)
The External Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt Trigger input with
an additional glitch filter. Reset pulses that are longer
than the minimum pulse width will generate a Reset.
Refer to Section 27.0 “Electrical Characteristics” for
minimum pulse width specifications. The External
Reset (MCLR) pin (EXTR) bit in the Reset Control
(RCON) register is set to indicate the MCLR Reset.
6.4.1
EXTERNAL SUPERVISORY
CIRCUIT
Many systems have external supervisory circuits that
generate Reset signals to reset multiple devices in the
system. This external Reset signal can be directly
connected to the MCLR pin to reset the device when
the rest of system is reset.
6.4.2 INTERNAL SUPERVISORY CIRCUIT
When using the internal power supervisory circuit to
reset the device, the External Reset pin (MCLR) should
be tied directly or resistively to VDD. In this case, the
MCLR pin will not be used to generate a Reset. The
External Reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.5 Software RESET Instruction (SWR)
Whenever the RESET instruction is executed, the
device will assert SYSRST, placing the device in a
special Reset state. This Reset state will not
re-initialize the clock. The clock source in effect prior to
the RESET instruction will remain. SYSRST is released
at the next instruction cycle and the Reset vector fetch
will commence.
The Software Reset (SWR) flag (instruction) in the
Reset Control (RCON<6>) register is set to indicate
the Software Reset.
6.6 Watchdog Timer Time-out Reset
(WDTO)
Whenever a Watchdog Timer Time-out Reset occurs,
the device will asynchronously assert SYSRST. The
clock source will remain unchanged. A WDT time-out
during Sleep or Idle mode will wake-up the processor,
but will not reset the processor.
The Watchdog Timer Time-out (WDTO) flag in the
Reset Control (RCON<4>) register is set to indicate
the Watchdog Timer Reset. Refer to Section 24.4
“Watchdog Timer (WDT)” for more information on
the Watchdog Timer Reset.
6.7 Trap Conflict Reset
If a lower priority hard trap occurs while a higher
priority trap is being processed, a hard Trap Conflict
Reset occurs. The hard traps include exceptions of
Priority Level 13 through Level 15, inclusive. The
address error (Level 13) and oscillator error (Level 14)
traps fall into this category.
The Trap Reset (TRAPR) flag in the Reset Control
(RCON<15>) register is set to indicate the Trap Conflict
Reset. Refer to Section 7.0 “Interrupt Controller” for
more information on Trap Conflict Resets.
6.8 Illegal Condition Device Reset
An illegal condition device Reset occurs due to the
following sources:
• Illegal Opcode Reset
• Uninitialized W Register Reset
• Security Reset
The Illegal Opcode or Uninitialized W Access Reset
(IOPUWR) flag in the Reset Control (RCON<14>) register
is set to indicate the illegal condition device Reset.
6.8.1 ILLEGAL OPCODE RESET
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
The Illegal Opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the Illegal Opcode Reset, use only the lower 16 bits of
each program memory section to store the data values.
The upper 8 bits should be programmed with 3Fh,
which is an illegal opcode value.
6.8.2 UNINITIALIZED W REGISTER RESET
Any attempt to use the uninitialized W register as an
Address Pointer will reset the device. The W register
array (with the exception of W15) is cleared during all
Resets and is considered uninitialized until written to.
6.8.3 SECURITY RESET
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a
protected segment (boot and secure segment), that
operation will cause a Security Reset.
The PFC occurs when the Program Counter is reloaded
as a result of a call, jump, computed jump, return, return
from subroutine or other form of branch instruction.
The VFC occurs when the Program Counter is
reloaded with an interrupt or trap vector.
Refer to Section 24.8 “Code Protection and
CodeGuard™ Security” for more information on
Security Reset.
DS70591E-page 120
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