DSPIC33FJ32GS406_12 Datasheet, PDF (201/456 Pages) Microchip Technology – 16-Bit Digital Signal Controllers with High-Speed PWM, ADC and Comparators

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
10.0 POWER-SAVING FEATURES
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 9. “Watchdog
Timer and Power-Saving Modes”
(DS70196) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices provide
the ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower
consumed power. Devices can manage power
consumption in four different ways:
• Clock Frequency
• Instruction-Based Sleep and Idle modes
• Software Controlled Doze mode
• Selective Peripheral Control in Software
Combinations of these methods can be used to
selectively tailor an application’s power consumption
while still maintaining critical application features, such
as timing-sensitive communications.
10.1 Clock Frequency and Clock
Switching
The devices allow a wide range of clock frequencies to
be selected under application control. If the system
clock configuration is not locked, users can choose
low-power or high-precision oscillators by simply
changing the NOSCx bits (OSCCON<10:8>). The
process of changing a system clock during operation,
as well as limitations to the process, are discussed in
more detail in Section 9.0 “Oscillator
Configuration”.
10.2 Instruction-Based Power-Saving
Modes
The devices have two special power-saving modes that
are entered through the execution of a special PWRSAV
instruction. Sleep mode stops clock operation and halts all
code execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. The assembler syntax of the PWRSAV
instruction is shown in Example 10-1.
Note:
SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to wake-up.
10.2.1 SLEEP MODE
The following occurs in Sleep mode:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption is reduced to a
minimum, provided that no I/O pin is sourcing
current.
• The Fail-Safe Clock Monitor does not operate,
since the system clock source is disabled.
• The LPRC clock continues to run in Sleep mode if
the WDT is enabled.
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Some device features or peripherals may continue
to operate. This includes the items such as the
input change notification on the I/O ports or
peripherals that use an external clock input.
• Any peripheral that requires the system clock
source for its operation is disabled.
The device will wake-up from Sleep mode on any of
these events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
; Put the device into SLEEP mode
; Put the device into IDLE mode
 2009-2012 Microchip Technology Inc.
DS70591E-page 201