PIC16F7X Datasheet, PDF (20/174 Pages) Microchip Technology – 28/40-Pin 8-Bit CMOS FLASH Microcontrollers

PIC16F7X
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Details
on page
Bank 2
100h⁽⁴⁾ INDF
101h TMR0
102h⁽⁴⁾ PCL
103h^{(4) STATUS}
104h⁽⁴⁾ FSR
105h —
106h PORTB
107h —
108h —
109h —
10Ah^(1,4) PCLATH
10Bh⁽⁴⁾ INTCON
10Ch PMDATA
10Dh PMADR
10Eh PMDATH
10Fh PMADRH
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
Program Counter (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
Unimplemented
PORTB Data Latch when written: PORTB pins when read
Unimplemented
Unimplemented
Unimplemented
—
—
— Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE TMR0IE
INTE
RBIE TMR0IF INTF
RBIF
Data Register Low Byte
Address Register Low Byte
—
— Data Register High Byte
—
—
— Address Register High Byte
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
—
xxxx xxxx
—
—
—
---0 0000
0000 000x
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
27, 96
45, 96
26, 96
19, 96
27, 96
—
34, 96
—
—
—
21, 96
23, 96
29, 97
29, 97
29, 97
29, 97
Bank 3
180h⁽⁴⁾ INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27, 96
181h OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 20, 44, 96
182h^{(4) PCL}
Program Counter (PC) Least Significant Byte
0000 0000 26, 96
183h⁽⁴⁾ STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 19, 96
184h^{(4) FSR}
Indirect Data Memory Address Pointer
xxxx xxxx 27, 96
185h —
Unimplemented
—
—
186h TRISB
PORTB Data Direction Register
1111 1111 34, 96
187h —
Unimplemented
—
—
188h —
Unimplemented
—
—
189h —
Unimplemented
—
—
18Ah^(1,4) PCLATH
—
—
— Write Buffer for the upper 5 bits of the Program Counter
---0 0000 21, 96
18Bh⁽⁴⁾ INTCON
GIE
PEIE TMR0IE
INTE
RBIE TMR0IF INTF
RBIF 0000 000x 23, 96
18Ch PMCON1
— ⁽⁶⁾
—
—
—
—
—
—
RD 1--- ---0 29, 97
18Dh —
Unimplemented
—
18Eh —
Reserved maintain clear
0000 0000
18Fh —
Reserved maintain clear
0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (CALL or GOTO).
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
DS30325B-page 18
 2002 Microchip Technology Inc.