PIC16F7X Datasheet, PDF (18/174 Pages) Microchip Technology – 28/40-Pin 8-Bit CMOS FLASH Microcontrollers

PIC16F7X
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Details
on page
Bank 0
00h⁽⁴⁾ INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27, 96
01h
TMR0
Timer0 Module Register
xxxx xxxx 45, 96
02h⁽⁴⁾ PCL
Program Counter (PC) Least Significant Byte
0000 0000 26, 96
03h⁽⁴⁾ STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 19, 96
04h⁽⁴⁾ FSR
Indirect Data Memory Address Pointer
xxxx xxxx 27, 96
05h
PORTA
—
— PORTA Data Latch when written: PORTA pins when read
--0x 0000 32, 96
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx 34, 96
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx 35, 96
08h⁽⁵⁾ PORTD
PORTD Data Latch when written: PORTD pins when read
xxxx xxxx 36, 96
09h⁽⁵⁾ PORTE
—
—
—
—
—
RE2
RE1
RE0 ---- -xxx 39, 96
0Ah^(1,4) PCLATH
—
—
— Write Buffer for the upper 5 bits of the Program Counter
---0 0000 26, 96
0Bh⁽⁴⁾ INTCON
GIE
PEIE TMR0IE
INTE
RBIE TMR0IF INTF
RBIF 0000 000x 21, 96
0Ch
PIR1
PSPIF⁽³⁾ ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 23, 96
0Dh
PIR2
—
—
—
—
—
—
—
CCP2IF ---- ---0 24, 96
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 50, 96
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 50, 96
10h
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 47, 96
11h
TMR2
Timer2 Module Register
0000 0000 52, 96
12h
T2CON
— TOUTPS3 TOUTPS2 TOUTPS TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 52, 96
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx 64, 68, 96
14h
SSPCON
WCOL SSPOV SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 61, 96
15h
CCPR1L
Capture/Compare/PWM Register1 (LSB)
xxxx xxxx 56, 96
16h
CCPR1H
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx 56, 96
17h
CCP1CON
—
—
CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 54, 96
18h
RCSTA
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D 0000 -00x 70, 96
19h
TXREG
USART Transmit Data Register
0000 0000 74, 96
1Ah
RCREG
USART Receive Data Register
0000 0000 76, 96
1Bh
CCPR2L
Capture/Compare/PWM Register2 (LSB)
xxxx xxxx 58, 96
1Ch
CCPR2H
Capture/Compare/PWM Register2 (MSB)
xxxx xxxx 58, 96
1Dh
CCP2CON
—
—
CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 54, 96
1Eh
ADRES
A/D Result Register Byte
xxxx xxxx 88, 96
1Fh
ADCON0
ADCS1 ADCS0 CHS2
CHS1
CHS0
GO/
DONE
—
ADON 0000 00-0 83, 96
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (CALL or GOTO).
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
DS30325B-page 16
 2002 Microchip Technology Inc.