PIC16F7X Datasheet, PDF (15/174 Pages) Microchip Technology – 28/40-Pin 8-Bit CMOS FLASH Microcontrollers

PIC16F7X
2.0 MEMORY ORGANIZATION
There are two memory blocks in each of these
PICmicro^® MCUs. The Program Memory and Data
Memory have separate buses so that concurrent
access can occur and is detailed in this section. The
Program Memory can be read internally by user code
(see Section 3.0).
Additional information on device memory may be found
in the PICmicro Mid-Range Reference Manual
(DS33023).
2.1 Program Memory Organization
The PIC16F7X devices have a 13-bit program counter
capable of addressing an 8K word x 14-bit program
memory space. The PIC16F77/76 devices have
8K words of FLASH program memory and the
PIC16F73/74 devices have 4K words. The program
memory maps for PIC16F7X devices are shown in
Figure 2-1. Accessing a location above the physically
implemented address will cause a wraparound.
The RESET Vector is at 0000h and the Interrupt Vector
is at 0004h.
2.2 Data Memory Organization
The Data Memory is partitioned into multiple banks,
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits:
RP1:RP0
Bank
00
0
01
1
10
2
11
3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
2.2.1
GENERAL PURPOSE REGISTER
FILE
The register file (shown in Figure 2-2 and Figure 2-3)
can be accessed either directly, or indirectly, through
the File Select Register FSR.
FIGURE 2-1:
PROGRAM MEMORY MAPS AND STACKS FOR PIC16F7X DEVICES
PIC16F76/77
PIC16F73/74
PC<12:0>
CALL, RETURN
13
RETFIE, RETLW
Stack Level 1
Stack Level 2
PC<12:0>
CALL, RETURN
13
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
Stack Level 8
On-Chip
Program
Memory
RESET Vector
Interrupt Vector
Page 0
Page 1
Page 2
Page 3
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
17FFh
1800h
1FFFh
On-Chip
Program
Memory
RESET Vector
Interrupt Vector
Page 0
Page 1
Unimplemented
Read as ‘0’
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
1FFFh
 2002 Microchip Technology Inc.
DS30325B-page 13