PIC16F7X Datasheet, PDF (19/174 Pages) Microchip Technology – 28/40-Pin 8-Bit CMOS FLASH Microcontrollers

PIC16F7X
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Details
on page
Bank 1
80h⁽⁴⁾ INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27, 96
81h
OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 20, 44, 96
82h⁽⁴⁾ PCL
Program Counter’s (PC) Least Significant Byte
0000 0000 26, 96
83h^{(4) STATUS}
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 19, 96
84h⁽⁴⁾ FSR
Indirect data memory address pointer
xxxx xxxx 27, 96
85h
TRISA
—
— PORTA Data Direction Register
--11 1111 32, 96
86h
TRISB
PORTB Data Direction Register
1111 1111 34, 96
87h
TRISC
PORTC Data Direction Register
1111 1111 35, 96
88h⁽⁵⁾ TRISD
PORTD Data Direction Register
1111 1111 36, 96
89h^{(5) TRISE}
IBF
OBF
IBOV PSPMODE
—
PORTE Data Direction Bits
0000 -111 38, 96
8Ah^(1,4) PCLATH
—
—
— Write Buffer for the upper 5 bits of the Program Counter
---0 0000 21, 96
8Bh^{(4) INTCON}
GIE
PEIE TMR0IE
INTE
RBIE TMR0IF INTF
RBIF 0000 000x 23, 96
8Ch
PIE1
PSPIE⁽³⁾ ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 22, 96
8Dh
PIE2
—
—
—
—
—
—
—
CCP2IE ---- ---0 24, 97
8Eh
PCON
—
—
—
—
—
—
POR
BOR ---- --qq 25, 97
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
91h
—
Unimplemented
—
—
92h
PR2
Timer2 Period Register
1111 1111 52, 97
93h
SSPADD
Synchronous Serial Port (I²C mode) Address Register
0000 0000 68, 97
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF 0000 0000 60, 97
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH TRMT
TX9D 0000 -010 69, 97
99h
SPBRG
Baud Rate Generator Register
0000 0000 71, 97
9Ah
—
Unimplemented
—
9Bh
—
Unimplemented
—
9Ch
—
Unimplemented
—
9Dh
—
Unimplemented
—
9Eh
—
Unimplemented
—
9Fh
ADCON1
—
—
—
—
—
PCFG2 PCFG1 PCFG0 ---- -000 84, 97
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (CALL or GOTO).
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
 2002 Microchip Technology Inc.
DS30325B-page 17