MIC2310_08 Datasheet, PDF (31/34 Pages) Micrel Semiconductor – Single-FET, Constant Power-Limit Hot Swap Controller

Micrel, Inc.
UVLO and OVP Operation
The system can be protected against an under-
voltage condition or an over-voltage condition on the
V_CC supply by using an external resistor divider and
the UVLO and OVP pins, respectively. Figure 17
illustrates the timing of the GATE and digital pin
outputs when the input supply crosses the UVLO and
OVP thresholds. When the voltage applied to the
UVLO pin is less than the V_UVLOL threshold voltage or
the voltage applied to the OVP pin is greater than the
MIC2310
V_OVPH threshold voltage, the GATE drive circuitry is
disabled, the GATE fault-mode pull-down current sink
is enabled, and the DISCH output goes high.
Increasing V_CC such that the voltage applied to the
UVLO pin increases above V_UVLOH or decreasing V_CC
such that the voltage applied to the OVP decreases
below V_OVPL re-enables the GATE drive circuit and
forces the DISCH output low, allowing the controller to
return to normal operation.
V_CC & V_REG
ENABLE
GATE
V_OUT
VVREG(UVLOH)
VGSPGH
VPGH
VGSPGH
VPGL
VPGH
VGSPGH
VPGL
VPGH
I_LOAD
UVLO
OVP
tPOR
PWRGD
DISCH
UVLOL
UVLOH
OVPH
OVPL
Figure 17. UVLO and OVP Operation
July 2008
31
M9999-070108-A