MIC2310_08 Datasheet, PDF (30/34 Pages) Micrel Semiconductor – Single-FET, Constant Power-Limit Hot Swap Controller

Micrel, Inc.
Open GNDSENSE Detector Trips CB
In order to protect the system from the result of an
open GNDSENSE pin, the controller incorporates an
open GNDSENSE detection scheme. An open
GNDSENSE pin could result in the effective primary
OC detection threshold being at an unsafe level. The
timing diagram in Figure 16 describes the operation of
this function. With the applied V_CC supply high such
that the internal V_REG voltage is above the controller’s
V_VREG(UVLOH) threshold voltage, an elapsed POR timer,
and with the application of an ENABLE LOW-to-HIGH
transition, the GATE drive circuitry is enabled and the
GATE voltage begins to rise. As the external
MOSFET turns ON, the SOURCE voltage begins to
rise also and the LOADSENSE voltage follows the
SOURCE voltage. Normally, the GNDSENSE pin
MIC2310
would remain at 0V. However, if the GNDSENSE pin
is open, the GNDSENSE voltage will rise due to the
load of other internal circuitry. An open GNDSENSE
pin is detected by comparing the voltage at the
GNDSENSE pin to the voltage at the AGND pin. Once
the voltage at the GNDSENSE pin differs from the
voltage at the AGND pin by V_THGNDSENSE, a circuit
breaker is tripped, the GATE drive circuitry is
disabled, the GATE fault-mode pull-down current sink
is enabled, and the DISCH output goes high. This
circuit breaker can be reset, such that the GATE drive
circuitry can be re-enabled, by either a HIGH-to-LOW
transition on ENABLE or turning off the V_CC supply
voltage to the controller such that V_REG falls below the
controller’s V_VREG(UVLOL) threshold voltage.
V_CC & V_REG
ENABLE
VVREG(UVLOH)
GATE
V_OUT
I_LOAD
GNDSENSE
PWRGD
GNDSENSE OPEN
VTHGNDSENSE
tPOR
VVREG(UVLOL)
VVREG(UVLOH)
VGSPGH
VPGH
GNDSENSE CONNECTED
tPOR
DISCH
Figure 16. Open GNDSENSE Detector Trips CB
July 2008
30
M9999-070108-A