MIC2310_08 Datasheet, PDF (18/34 Pages) Micrel Semiconductor – Single-FET, Constant Power-Limit Hot Swap Controller

Micrel, Inc.
VCC & VREG
ENABLE
GATE
V_OUT
I_LOAD
CRETRY
PWRGD
I_FLT
DISCH
VCC = 12V, nominal
VVREG(UVLOH)
VREG = 5V, nominal
VGSPGH
VPGH
IPOC
tPOR
VGSPGH
tPOC
VPGL
tRETRY
MIC2310
Figure 6. Primary Overcurrent Fault with Auto-Retry to Reset the Circuit Breaker
HW_FLT Digital Output Asserted by a MOSFET DG
Short with ENABLE = LOW
In order to protect the system from the result of the
installation of a damaged MOSFET on the PCB, the
controller incorporates a MOSFET shorted DG
detection scheme whose operation is described in
Figure 7. With the applied V_CC supply high such that
the internal V_REG voltage is above the controller’s
V_VREG(UVLOH) threshold voltage, an elapsed POR timer,
and with the ENABLE input LOW, a weak current sink
at the GATE pin attempts to hold the GATE voltage at
0V. If there is a DG short on the MOSFET, the weak
current sink is not capable of holding the voltage at 0V
as the GATE voltage tracks the MOSFET’s DRAIN
voltage. The voltage monitor circuit at the controller’s
GATE pin will be triggered once the GATE voltage
crosses the V_GATEFT(EXT) threshold voltage. The
HW_FLT digital output is subsequently asserted within
a delay approximately equal to the delay in the logic
circuits – no additional timing circuit is required. To
clear the latched GATE voltage monitor circuit and to
reset the HW_FLT digital output, the applied V_CC
supply voltage must fall such that V_REG is below the
controller’s V_VREG(UVLOL) threshold voltage.
July 2008
18
M9999-070108-A