MIC2310_08 Datasheet, PDF (29/34 Pages) Micrel Semiconductor – Single-FET, Constant Power-Limit Hot Swap Controller

Micrel, Inc.
Open LOADSENSE Detector Trips CB
In order to protect the system from the result of an
open LOADSENSE pin, the controller incorporates an
open LOADSENSE detection scheme. An open
LOADSENSE pin could result in the effective primary
OC detection threshold being at an unsafe level. The
timing diagram in Figure 15 describes the operation of
this function. With the applied V_CC supply high such
that the internal V_REG voltage is above the controller’s
V_VREG(UVLOH) threshold voltage, an elapsed POR timer,
and with the application of an ENABLE LOW-to-HIGH
transition, the GATE drive circuitry is enabled and the
GATE voltage begins to rise. As the external
MOSFET turns ON, the SOURCE voltage begins to
rise also. Normally, the LOADSENSE voltage would
rise with the SOURCE voltage. However, if the
MIC2310
LOADSENSE pin is open, the LOADSENSE voltage
will remain at a lower voltage due to the load of other
internal circuitry. An open LOADSENSE pin is
detected by comparing the voltage at the SOURCE
pin to the voltage at the LOADSENSE pin. Once the
voltage at the SOURCE pin differs from the voltage at
the LOADSENSE pin by V_THLOADSENSE, a circuit
breaker is tripped, the GATE drive circuitry is
disabled, the GATE fault-mode pull-down current sink
is enabled, and the DISCH output goes high. This
circuit breaker can be reset, such that the GATE drive
circuitry can be re-enabled, by either a HIGH-to-LOW
transition on ENABLE or turning off the V_CC supply
voltage to the controller such that V_REG falls below the
controller’s V_VREG(UVLOL) threshold voltage.
V_CC & V_REG
ENABLE
VVREG(UVLOH)
GATE
V_OUT
I_LOAD
LOADSENSE
tPOR
PWRGD
VVREG(UVLOL)
VTHLOADSENSE
LOADSENSE OPEN
VVREG(UVLOH)
VGSPGH
VPGH
LOADSENSE CONNECTED
tPOR
DISCH
July 2008
Figure 15. Open LOADSENSE Detector Trips CB
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M9999-070108-A