MIC2310_08 Datasheet, PDF(27/34 Page) Micrel Semiconductor – Single-FET, Constant Power-Limit Hot Swap Controller

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MIC2310_08 Datasheet, PDF (27/34 Pages) Micrel Semiconductor – Single-FET, Constant Power-Limit Hot Swap Controller

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Micrel, Inc.

Shorted CPRIMARY Detector Asserts HW_FLT After

Primary OC Event

The diagram in Figure 14 illustrates the behavior of

the controller to a shorted CPRIMARY capacitor condition

after steady-state operation is achieved via a nominal

start-up and after a primary OC event has occurred.

As described previously, during a primary OC event,

the CPRIMARY capacitor is discharged as part of setting

the primary OC detector response time, tPOC. In order

to prevent a false CPRIMARY short detection from

occurring while the CPRIMARY pin is being

intentionally discharged, the CPRIMARY short detection

circuit is disabled when the primary OC detector

detects an overcurrent. In addition, the CPRIMARY short

detection circuit is not re-enabled until after a time

delay, tSCPDETPOR, once the primary OC detector no

longer detects an overcurrent. This delay time should

allow a capacitor of reasonable size to be charged

back up above VPRIH, even if it has been discharged to

0V, such that a false CPRIMARY short is not indicated

MIC2310

when the CPRIMARY short detection circuitry is re-

enabled.

In the timing diagram, CPRIMARY becomes shorted

during the primary OC event. When the CPRIMARY

pin voltage falls below VPRIL, the tPOCSENSE timer is

enabled. Once this timer times out, the circuit breaker

is tripped, I_FLT is asserted, the GATE drive circuitry

is disabled, the GATE fault-mode pull-down current

sink is enabled, and the DISCH output goes high. As

the external MOSFET is turned OFF, the output

current drops and an overcurrent condition is no

longer detected. This initiates the tSCPDETPOR timer.

Since CPRIMARY does not charge back up above VPRIH

before this timer expires, HW_FLT is asserted after

the tSCPDETPOR time. To repair the damaged CPRIMARY

capacitor and reset the HW_FLT digital output, the

service processor instructs the main supply to turn off

the VCC supply voltage to the controller such that VREG

falls below the controllerâs VVREG(UVLOL) threshold

voltage.

July 2008

M9999-070108-A

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