MIC2310_08 Datasheet, PDF(13/34 Page) Micrel Semiconductor – Single-FET, Constant Power-Limit Hot Swap Controller

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MIC2310_08 Datasheet, PDF (13/34 Pages) Micrel Semiconductor – Single-FET, Constant Power-Limit Hot Swap Controller

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Micrel, Inc.

Functional Description

Basic Startup Cycle

The basic operation of the MIC2310 is illustrated

below in Figure 2 from a cold-start condition. With the

applied VCC supply low such that the internal VREG

voltage is less than the MIC2310âs internal

VVREG(UVLOH) threshold voltage, all state machines are

reset, all voltage and current monitor subcircuits are

OFF, and the GATE drive circuit is disabled. Digital

inputs and all open-drain digital outputs are inactive.

When the applied VCC supply rises such that the

internal VREG voltage is above the controllerâs

VVREG(UVLOH) threshold voltage, the tPOR counter circuit

commences. Once the timer terminates, all internal

state machines are activated, the CPRIMARY short

detection circuit is ON and the DG & DS MOSFET

short detection circuits are ON if ENABLE is LOW.

The I_FLT, PWRGD, and HW_FLT outputs are valid.

Upon the application of an ENABLE LOW-to-HIGH

transition after the tPOR delay, or at the end of the tPOR

delay if ENABLE is already HIGH, a nominal start-up

commences where the dID/dt-controlled inrush current

(by dID/dt = 17.6x10-3 Ã ISLEW / (RSENSE ÃCSLEW)) is

permitted to exceed the IPOC threshold for tPOC, until

VCC

+12V, nominal

VVREGUVLOH

VREG = 5V, nominal

MIC2310

there is sufficient charge stored on the load capacitor

as evidenced by the output load voltage profile. Note

that the secondary overcurrent detection threshold

(ISOC) is set externally at the controllerâs S[1:0] pins.

Once the inrush current exceeds the ISOC threshold,

the circuit breaker trips without delay and the

MIC2310 controller shuts down the output. If the

inrush current profile does not cause either of the OC

detection circuits to trip the circuit breaker and assert

the I_FLT digital output, the controller will assert the

PWRGD digital output when the output load voltage is

higher than the controllerâs VPGH threshold voltage and

the VGS of the external MOSFET is higher than the

controllerâs VGSPGH threshold voltage. Due to the low

RDS(ON) of the external MOSFET, the output load

voltage rises with the GATE voltage as the VGS of the

MOSFET reaches its threshold voltage. Once the

output load voltage stabilizes near the VCC supply

voltage, the VGS of the external MOSFET increases

above its threshold voltage and eventually exceeds

VGSPGH. The PWRGD output asserts to signal that the

external MOSFET is fully enhanced and ready for the

application of the full load.

ENABLE

GATE

Primary & Secondary

OC Detector Armed

VGSPGH

Power

Not Good

VOUT

ILOAD

dID/dt

Control

by CSLEW

ât = f(CGATE,VTH(FET))

Power

Good

t POC

I SOC

I POC

PWRGD

tPOR

ISOC = VCBS/RSENSE

set by S[1:0]

IPOC = VCBP/RSENSE

Peak inrush current = f(CSLEW, CLOAD)

tPOC = f(CPRIMARY)

VPGL

I_FLT

Figure 2. Basic Startup Cycle

July 2008

M9999-070108-A

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