MIC2310_08 Datasheet, PDF (16/34 Pages) Micrel Semiconductor – Single-FET, Constant Power-Limit Hot Swap Controller

Micrel, Inc.
Charging Load by dI_D/dt – Primary OC Trips CB
after t_POC and CB Reset by Toggling ENABLE
HIGH-to-LOW
Figure 5 illustrates the behavior of the controller to an
OC event after the primary and secondary OC
detection circuits have been armed (upon the
application of an ENABLE LOW-to-HIGH transition
and after t_POR). In this example, the load capacitor is
charged at a controlled dI_D/dt rate. Steady-state
operation is not achieved as the controlled inrush
profile causes the primary OC detector to trigger at
I_POC and continues charging when the t_POCSENSE timer
terminates. Note that the controller’s PWRGD digital
output does not assert because the output load
MIC2310
voltage profile at no time rises higher than the
controller’s V_PGH threshold voltage and the V_GS of the
external MOSFET does not rise higher than the
controller’s V_GSPGH threshold voltage.
Once the circuit breaker has latched, the I_FLT digital
output is asserted. When the circuit breaker is tripped
by either the primary OC or secondary OC detectors),
applying a HIGH-to-LOW transition on the ENABLE
pin will reset the circuit breaker. At a delay defined by
t_CBRESET, the internal circuit breaker is reset and is
indicated when the I_FLT digital output becomes de-
asserted. The earliest a LOW-to-HIGH transition at
ENABLE is permitted to initiate a new start-up
sequence is defined by the t_ENLPW timing specification.
VCC = 12V, nominal
VVREG(UVLOH) = +4.25V
VREG = 5V, nominal
Figure 5. dI_D/dt Load Charge Profile w/ Primary OC Circuit Breaker (CB) Trip w/ CB Reset
July 2008
16
M9999-070108-A