MIC2310_08 Datasheet, PDF (22/34 Pages) Micrel Semiconductor – Single-FET, Constant Power-Limit Hot Swap Controller

Micrel, Inc.
HW_FLT Asserted by MOSFET DS Short after
Steady-state Operation then a Fault Condition
Figure 10 illustrates the behavior of the controller to a
shorted DS MOSFET condition after steady-state
operation is achieved via a nominal start-up. With the
occurrence of one of the following fault conditions –
UVLO, OVP, primary OC, secondary OC, open
LOADSENSE, or open GNDSENSE - the GATE drive
circuit is disabled, the GATE fault-mode pull-down
current sink is enabled, the DISCH output goes high,
and the t_DS-SSFAULT timer is started. The occurrence of
a primary OC fault condition is shown here. The
MIC2310
voltage monitor circuit for the controller’s SOURCE
pin is also enabled. If there is a DS short, the voltage
at the source will not drop to 0V even though the
GATE is OFF. If the output voltage at the SOURCE
pin remains higher than the controller’s V_SRCFT(EXT)
threshold voltage when the t_DS-SSFAULT timer
terminates, the HW_FLT digital output is asserted. To
repair the damaged MOSFET and to reset the
HW_FLT digital output and the controller, the service
processor instructs the main supply to turn off the V_CC
supply voltage to the controller such that V_REG falls
below the controller’s V_VREG(UVLOL) threshold voltage.
V_CC & V_REG
ENABLE
GATE
V_OUT
I_LOAD
PWRGD
I_FLT
HW_FLT
DISCH
VVREG(UVLOH)
tPOR
VVREG(UVLOL)
VVREG(UVLOH)
VGSPGH
VPGH
DG Short
VGSPGH
tPOC
VSRCFT(EXT)
VPGL
tPOR
tDS-SSFAULT
Figure 10. HW_FLT Asserted by a MOSFET DS Short after Steady-State Operation then a Fault Condition
July 2008
22
M9999-070108-A