71M6543F Datasheet, PDF (81/157 Pages) Maxim Integrated Products – Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation

71M6543F/H and 71M6543G/GH Data Sheet
3.3.2 IC Behavior at Low Battery Voltage
When system power is not present, the 71M6543 relies on the VBAT pin for power. If the VBAT voltage is
not sufficient to maintain VDD at 2.0 VDC or greater, the MPU cannot operate reliably. Low VBAT voltage
can occur while the part is operating in BRN mode, or while it is dormant in SLP or LCD mode. Two cases
can be distinguished, depending on MPU code:
• Case 1: System power is not present, and the part is waking from SLP or LCD mode. In this case,
the hardware checks the value of VDD to determine if processor operation is possible. If it is not
possible, the part configures itself for BRN operation, and holds the processor in reset (WAKE=0). In
this mode, VBAT powers the 1.0 VDC reference for the LCD system, the VDD regulator, the PLL, and
the fault comparator. The part remains in this waiting mode until VDD becomes high due to system
power being applied or the VBAT battery being replaced or recharged.
• Case 2: The part is operating under VBAT power and VSTAT[2:0] (SFR 0xF9[2:0]) becomes 101,
indicating that VDD falls below 2.0 VDC. In this case, the firmware has two choices:
1) One choice is to assert the SLEEP bit (I/O RAM 0x28B2[7]) immediately. This assertion preserves
the remaining charge in VBAT. Of course, if the battery voltage is not increased, the 71M6543
enters Case 1 as soon as it tries to wake up.
2) The alternative choice is to enter the waiting mode described in Case 1 immediately. Specifically,
if the firmware does not assert the SLEEP bit, the hardware resets the processor four CE32 clock
cycles (i.e. 122 µs) after VSTAT[2:0] becomes 101 and, as described in Case 1, it begins waiting
for VDD to become greater than 2.0 VDC. The MPU wakes up when system power returns, or
when VDD becomes greater than 2.0 VDC.
In either case, when VDD recovers, and when the MPU wakes up, the WF_BADVDD flag (I/O RAM 0x28B0[2])
can be read to determine that the processor is recovering from a bad VBAT condition. The WF_BADVDD
flag remains set until the next time WAKE falls. This flag is independent of the other WF flags.
In all cases, low VBAT voltage does not corrupt RTC operation, the state of NV memory, or the state of
non-volatile memory. These circuits depend on the VBAT_RTC pin for power.
3.3.3 Reset Sequence
When the RESET pin is pulled high, all digital activity in the chip stops, with the exception of the oscillator
and RTC. Additionally, all I/O RAM bits are forced to their RST state. A reliable reset does not occur until
RESET has been high at least for 2 µs. Note that TMUX and the RTC are not reset unless the TEST pin
is pulled high while RESET is high.
The RESET control bit (I/O RAM 0x 2200[3]) performs an identical reset to the RESET pin except that a
significantly shorter reset timer is used.
Once initiated, the reset sequence waits until the reset timer times out. The time out occurs in 4100
CE32 cycles (125 ms), at which time the MPU begins executing its pre-boot and boot sequences from
address 0x0000. See 2.5.1.1 for a detailed description of the pre-boot and boot sequences.
If system power is not present, the reset timer duration is two CE32 cycles, at which time the MPU begins
executing in BRN mode, starting at address 0x0000.
A softer form of reset is initiated when the E_RST pin of the ICE interface is pulled low. This event causes
the MPU and other registers in the MPU core to be reset but does not reset the remainder of the
71M6543. It does not trigger the reset sequence. This type of reset is intended to reset the MPU
program, but not to make other changes to the chip’s state.
3.3.4 Watchdog Timer (WDT) Reset
The watchdog timer (WDT) is described in 2.5.13.
A status bit, WF_OVF (I/O RAM 0x28B0[4]), is set when a WDT overflow occurs. Similar to the other wake
flags, this bit is powered by the non-volatile supply and can be read by the MPU to determine if the part is
initializing after a WD overflow event or after a power-up. The WF_OVF bit is cleared by the RESET pin.
There is no internal digital state that could deactivate the WDT. For debug purposes, however, the WDT
can be disabled by raising the ICE_E pin to 3.3 VDC.
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