71M6543F Datasheet, PDF(7/157 Page) Maxim Integrated Products – Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation

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71M6543F Datasheet, PDF (7/157 Pages) Maxim Integrated Products – Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation

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71M6543F/H and 71M6543G/GH Data Sheet

Table 49: Data/Direction Registers and Internal Resources for SEGDIO0 to SEGDIO15........................ 60

Table 50: Data/Direction Registers for SEGDIO16 to SEGDIO31........................................................... 61

Table 51: Data/Direction Registers for SEGDIO32 to SEGDIO45........................................................... 61

Table 52: Data/Direction Registers for SEGDIO51 to SEGDIO55........................................................... 61

Table 53: LCD_VMODE Configurations .................................................................................................. 63

Table 54: LCD Configurations................................................................................................................ 64

Table 55: LCD Data Registers for SEGDIO46 to SEGDIO55.................................................................. 65

Table 56: EECTRL Bits for 2-pin Interface............................................................................................... 66

Table 57: EECTRL Bits for the 3-wire Interface ....................................................................................... 67

Table 58: SPI Transaction Fields ........................................................................................................... 69

Table 59: SPI Command Sequences ..................................................................................................... 70

Table 60: SPI Registers......................................................................................................................... 70

Table 61: TMUX[4:0] Selections ............................................................................................................ 73

Table 62: TMUX2[4:0] Selections........................................................................................................... 74

Table 63: Available Circuit Functions ..................................................................................................... 77

Table 64: VSTAT[2:0] (SFR 0xF9[2:0]) ................................................................................................... 80

Table 65: Wake Enable and Flag Bits .................................................................................................... 82

Table 66: Wake Bits .............................................................................................................................. 83

Table 67: Clear Events for WAKE flags.................................................................................................. 84

Table 68: GAIN_ADJn Compensation Channels (Figure 2, Figure 31, Table 1) ...................................... 91

Table 69: GAIN_ADJx Compensation Channels (Figure 3, Figure 32, Table 2) ...................................... 93

Table 70: I/O RAM Map â Functional Order, Basic Configuration ........................................................... 98

Table 71: I/O RAM Map â Functional Order ......................................................................................... 100

Table 72: I/O RAM Map â Alphabetical Order ...................................................................................... 104

Table 73: Info Page Trim Fuses........................................................................................................... 118

Table 74: CE EQU[2:0] Equations and Element Input Mapping ............................................................ 121

Table 75: CE Raw Data Access Locations ........................................................................................... 122

Table 76: CESTATUS Register.............................................................................................................. 123

Table 77: CESTATUS Bit Definitions...................................................................................................... 123

Table 78: CECONFIG Register............................................................................................................. 123

Table 79: CECONFIG Bit Definitions (CE RAM 0x20) ........................................................................... 124

Table 80: Sag Threshold, Phase Measurement, and Gain Adjust Control............................................. 125

Table 81: CE Transfer Variables (with Shunts)..................................................................................... 125

Table 82: CE Transfer Variables (with CTs) ......................................................................................... 126

Table 83: CE Energy Measurement Variables (with Shunts)................................................................. 126

Table 84: CE Energy Measurement Variables (with CTs) ..................................................................... 126

Table 85: Other Transfer Variables ...................................................................................................... 127

Table 86: CE Pulse Generation Parameters......................................................................................... 128

Table 87: CE Parameters for Noise Suppression and Code Version..................................................... 129

Table 88: CE Calibration Parameters................................................................................................... 130

Table 89: Absolute Maximum Ratings.................................................................................................. 133

Table 90: Recommended External Components .................................................................................. 134

Table 91: Recommended Operating Conditions................................................................................... 134

Table 92: Input Logic Levels ................................................................................................................ 135

Table 93: Output Logic Levels ............................................................................................................. 135

Table 94: Battery Monitor Performance Specifications (TEMP_BAT = 1) ............................................... 136

Table 95: Temperature Monitor............................................................................................................ 137

Table 96: Supply Current Performance Specifications.......................................................................... 138

Table 98: Internal Power Fault Comparators Performance Specifications............................................. 139

Table 99: 2.5 V Voltage Regulator Performance Specifications ............................................................ 139

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