71M6543F Datasheet, PDF(63/157 Page) Maxim Integrated Products – Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation

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71M6543F Datasheet, PDF (63/157 Pages) Maxim Integrated Products – Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation

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71M6543F/H and 71M6543G/GH Data Sheet

Table 52: LCD_VMODE Configurations

LCD_VMODE[1:0] LCD_EXT LDAC_E LCD_BSTE Description

External VLCD connected to the VLCD pin.

LCD boost is enabled. Maximum VLCD voltage is

2*V3P3L-1.

VLCD = max(2*V3P3L-1, 2.65(1+LCD_DAC[4:0]/31)

LCD boost is disabled. The maximum VLCD

voltage is V3P3L.

VLCD = max(V3P3L, 2.65(1+LCD_DAC[4:0]/31)

VLCD=V3P3L, the LCD DAC and LCD boost are dis-

abled. In LCD mode, this setting causes the lowest

battery current.

Notes:

1. LCD_EXT, LDAC_E and LCD_BSTE are 71M6543 internal signals which are decoded from

the LCD_VMODE[1:0] control field setting (I/O RAM 0x2401[7:6]). Each of these decoded signals,

when asserted, has the effect indicated in the description column above, and as summarized

below.

LCD_EXT : When set, the VLCD pin expects an external supply voltage

LDAC_E : When set, LCD DAC is enabled

LCD_BSTE : When set, the LCD boost circuit is enabled

2. V3P3L is an internal supply rail that is supplied from either the VBAT pin or the V3P3SYS pin,

depending on the V3P3SYS pin voltage. When the V3P3SYS pin drops below 3.0 VDC, the

71M6543 switches to BRN mode and V3P3L is sourced from the VBAT pin, otherwise V3P3L

is sourced from the V3P3SYS pin while in MSN mode.

When using the VLCD boost circuit, use care when setting the LCD_DAC[4:0] (I/O RAM 0x240D[4:0])

value to ensure that the LCD manufacturerâs recommended operating voltage specification is not

exceeded.

The voltage doubler is active in all LCD modes including the LCD mode when LCD_BSTE = 1. Current

dissipation in LCD mode can be reduced if the boost circuit is disabled and the LCD system is operated

directly from VBAT.

The LCD DAC uses a low-power reference and, within the constraints of VBAT and the voltage doubler,

generates a VLCD voltage of 2.65 VDC + 2.65 * LCD_DAC[4:0]/31. Two fuse bytes increase the accuracy

of the LCD_DAC. LCDADJ12 and LCDADJ0 indicate the actual VLCD output voltage when the DAC is

programmed to 12 and 0 respectively.

The LCD_BAT (I/O RAM 0x2402[7]) bit causes the LCD system to use the battery voltage in all power

modes. This may be useful when an external supply is available for the LCD system. The advantage of

connecting the external supply to VBAT, rather than VLCD is that the LCD DAC is still active.

If LCD_EXT = 1, the VLCD pin must be driven from an external source. In this case, the LCD DAC has

no effect.

The LCD system has the ability to drive up to six segments per SEG driver. If the display is configured with

six back planes, the 6-way multiplexing reduces the number of SEG pins required to drive a display and

therefore enhances the number of DIO pins available to the application. Refer to the LCD_MODE[2:0] field

(I/O RAM 0x2400[6:4]) settings (Table 53) for the different LCD multiplexing choices. If 5-state multiplexing

is selected, SEGDIO27 is converted to COM4. If 6-state multiplexing is selected, SEGDIO26 is converted

to COM5. These conversions override the SEG/DIO mapping of SEGDIO26 and SEGDIO27. Additionally,

independent of LCD_MODE[2:0], if LCD_ALLCOM = 1 (I/O RAM 0x2400[3]), then SEGDIO26 and

SEGDIO27 become COM4 and COM5 if their LCD_MAP[ ] bits are set.

The LCD_ON (I/O RAM 0x240C[0]) and LCD_BLANK (I/O RAM 0x240C[1]) bits are an easy way to either

blank the LCD display or turn it fully on. Neither bit affects the contents of the LCD data stored in the

LCDSEG_DIO[ ] registers. In comparison, LCD_RST (I/O RAM 0x240C[2]) clears all LCD data to zero.

LCD_RST affects only pins that are configured as LCD.

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