71M6543F Datasheet, PDF (53/157 Pages) Maxim Integrated Products – Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation

71M6543F/H and 71M6543G/GH Data Sheet
The default frequency is 32,768 RTCLK cycles per second. To shift the clock frequency by ∆ ppm,
RTC_P and RTC_Q are calculated using the following equation:
4 ⋅ RTC_P
+ RTC_Q
=
floor


32768 ⋅ 8
1+ ∆ ⋅10^−6
+ 0.5_

Conversely, the amount of ppm shift for a given value of 4RTC_P+RTC_Q is:
∆( ppm)
=


32768 ⋅ 8
4 ⋅ RTC_P + RTC_Q
−1_{} ⋅10⁶
For example, for a shift of -988 ppm, 4 ⋅ RTC_P + RTC_Q = 262403 = 0x40103. RTC_P[16:0] = 0x10040,
(I/O RAM 0x289B[2:0], 0x289C, 0x289D[7:2]) and RTC_Q[1:0] = 0x03 (I/O RAM 0x289D[1:0]. The default
values of RTC_P[16:0] and RTC_Q[1:0], corresponding to zero adjustment, are 0x10000 and 0x0, respectively.
Two settings for the TMUX2OUT test pin, PULSE_1S and PULSE_4S, are available for measuring and
calibrating the RTC clock frequency. These are waveforms of approximately 25% duty cycle with 1s or 4s
period.
Default values for RTCA_ADJ[6:0], RTC_P[16:0] and RTC_Q[1:0] should be nominal values, at
the center of the adjustment range. Un-calibrated extreme values (zero, for example) can cause
incorrect operation.
If the crystal temperature coefficient is known, the MPU can integrate temperature and correct the RTC
time as necessary. Alternatively, the characteristics can be loaded into an NV RAM and the OSC_COMP
(I/O RAM 0x28A0[5]) bit may be set. In this case, the oscillator is adjusted automatically, even in SLP
mode. See 2.5.4.4 RTC Temperature Compensation for details.
2.5.4.4 RTC Temperature Compensation
The 71M6543 can be configured to regularly measure die temperature, including in SLP and LCD modes
and while the MPU is halted. If enabled by OSC_COMP, this temperature information is automatically
used to correct for the temperature variation of the crystal. A table lookup method is used.
Table 44 shows I/O RAM registers involved in automatic RTC temperature compensation.
Table 44: I/O RAM Registers for RTC Temperature Compensation
Name
OSC_COMP
STEMP[10:3]
STEMP[2:0]
LKPADDR[6:0]
LKPAUTOI
LKPDAT[7:0]
LKP_RD
LKP_WR
Location
28A0[5]
2881[7:0]
2882[7:5]
2887[6:0]
2887[7]
2888[7:0]
2889[1]
2889[0]
Rst Wk Dir Description
0
0
R/W
Enables the automatic update of RTC_P[16:0] and
RTC_Q[1:0] every time the temperature is measured.
–
–
R
The result of the temperature measurement (10-bits
of magnitude data plus a sign bit).
0
0
R/W
The address for reading and writing the RTC lookup
RAM.
Auto-increment flag. When set, LKPADDR[6:0] auto
0
0
R/W
increments every time LKP_RD or LKP_WR is pulsed.
The incremented address can be read at
LKPADDR[6:0].
0
0
R/W
The data for reading and writing the RTC lookup
RAM.
Strobe bits for the RTC lookup RAM read and write.
When set, the LKPADDR[6:0] and LKPDAT registers
0 0 R/W are used in a read or write operation. When a strobe is
0 0 R/W set, it stays set until the operation completes, at which
time the strobe is cleared and LKPADDR[6:0] is
incremented if LKPAUTOI is set.
Referring to Figure 13 the table lookup method uses the 10-bits plus sign-bit value in STEMP[10:0]
right-shifted by two bits to obtain an 8-bit plus sign value (i.e., NV RAM Address = STEMP[10:0]/4). A
v1.2
© 2008–2011 Teridian Semiconductor Corporation
53