71M6543F Datasheet, PDF (5/157 Pages) Maxim Integrated Products – Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation

71M6543F/H and 71M6543G/GH Data Sheet
Figures
Figure 1: IC Functional Block Diagram ..................................................................................................... 9
Figure 2: AFE Block Diagram (Shunts: One-Local, Three-Remotes) ...................................................... 12
Figure 3. AFE Block Diagram (Four CTs)............................................................................................... 13
Figure 4: States in a Multiplexer Frame (MUX_DIV[3:0] = 6) .................................................................. 17
Figure 5: States in a Multiplexer Frame (MUX_DIV[3:0] = 7) .................................................................. 17
Figure 6: General Topology of a Chopped Amplifier............................................................................... 21
Figure 7: CROSS Signal with CHOP_E = 00........................................................................................... 21
Figure 8: RTM Timing ............................................................................................................................ 26
Figure 9. Pulse Generator FIFO Timing ................................................................................................. 28
Figure 10: Samples from Multiplexer Cycle (Frame)............................................................................... 29
Figure 11: Accumulation Interval............................................................................................................ 29
Figure 12: Interrupt Structure................................................................................................................. 46
Figure 13: Automatic Temperature Compensation ................................................................................. 54
Figure 14: Optical Interface.................................................................................................................... 58
Figure 15: Optical Interface (UART1) ..................................................................................................... 58
Figure 16: Connecting an External Load to DIO Pins ............................................................................. 60
Figure 17: LCD Waveforms ................................................................................................................... 65
Figure 18: 3-wire Interface. Write Command, HiZ=0.............................................................................. 67
Figure 19: 3-wire Interface. Write Command, HiZ=1.............................................................................. 68
Figure 20: 3-wire Interface. Read Command......................................................................................... 68
Figure 21: 3-Wire Interface. Write Command when CNT=0................................................................... 68
Figure 22: 3-wire Interface. Write Command when HiZ=1 and WFR=1.................................................. 68
Figure 23: SPI Slave Port - Typical Multi-Byte Read and Write operations.............................................. 70
Figure 24: Voltage, Current, Momentary and Accumulated Energy......................................................... 75
Figure 25: Operation Modes State Diagram ........................................................................................... 76
Figure 26: MPU/CE Data Flow............................................................................................................... 85
Figure 27: Resistive Voltage Divider (Voltage Sensing).......................................................................... 86
Figure 28. CT with Single-Ended Input Connection (Current Sensing).................................................... 86
Figure 29: CT with Differential Input Connection (Current Sensing) ........................................................ 86
Figure 30: Differential Resistive Shunt Connections (Current Sensing)................................................... 86
Figure 31: System Using Three-Remotes and One-Local (Neutral) Sensor ............................................ 87
Figure 32. System Using Current Transformers ..................................................................................... 88
Figure 33: I²C EEPROM Connection...................................................................................................... 94
Figure 34: Connections for UART0 ........................................................................................................ 94
Figure 35: Connection for Optical Components...................................................................................... 95
Figure 36: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right) ....... 96
Figure 37: External Components for the Emulator Interface ................................................................... 96
Figure 38. Trim Fuse Bit Mapping ........................................................................................................ 118
Figure 39: CE Data Flow: Multiplexer and ADC.................................................................................... 131
Figure 40: CE Data Flow: Scaling, Gain Control, Intermediate Variables for one Phase........................ 131
Figure 41: CE Data Flow: Squaring and Summation Stages................................................................. 132
Figure 42: Wh Error from 200 A to 0.1 A at 60 Hz, 240 VAC ......................Error! Bookmark not defined.
Figure 43: VARh Error from 200 A to 0.1 A at 60 Hz, 240 VAC...................Error! Bookmark not defined.
Figure 44: Wh Error from 200 A to 0.1 A at Various Frequencies (0° Load angle, 240 VAC)............. Error!
Bookmark not defined.
Figure 45: 100-pin LQFP Package Outline........................................................................................... 148
Figure 46: Pinout for the LQFP-100 Package....................................................................................... 149
Figure 47: I/O Equivalent Circuits......................................................................................................... 154
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