MAX11014_08 Datasheet, PDF (67/70 Pages) Maxim Integrated Products – Automatic RF MESFET Amplifier Drain-Current Controllers

Automatic RF MESFET Amplifier
Drain-Current Controllers
THD = 20 x log ^{V22 + V32 + V42 + V52 + V62}
V₁
where V₁ is the fundamental amplitude, and V₂ through
V₆ are the amplitudes of the first five harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest
spectral component.
ADC Channel-to-Channel Crosstalk
Bias the ON channel to midscale. Apply a full-scale sine-
wave test tone to all OFF channels. Perform an FFT on
the ON channel. ADC channel-to-channel crosstalk is
expressed in dB as the amplitude of the FFT spur at the
frequency associated with the OFF channel test tone.
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f₁ and
f₂, are present at the inputs. The intermodulation prod-
ucts are (f₁ ± f₂), (2 x f₁), (2 x f₂), (2 x f₁ ± f₂), (2 x f₂ ±
f₁). The individual input tone levels are at -7dBFS.
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC in such a way that the signal’s slew rate does not
limit the ADC’s performance. The input frequency is
then swept up to the point where the amplitude of the
digitized conversion result has decreased by -3dB.
Note that the track/hold (T/H) performance is usually
the limiting factor for the small-signal input bandwidth.
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
DAC Digital Feedthrough
DAC digital feedthrough is the amount of noise that
appears on the DAC output when the DAC digital con-
trol lines are toggled.
ADC Power-Supply Rejection
Power-supply rejection is defined as the shift in offset
error when the power supply is moved from the minimum
operating voltage to the maximum operating voltage.
DAC Power-Supply Rejection
DAC PSR is the amount of change in the converter’s
value at full scale as the power-supply voltage
changes from its nominal value. PSR assumes the
converter’s linearity is unaffected by changes in the
power-supply voltage.
Pin Configuration
TOP VIEW
36 35 34 33 32 31 30 29 28 27 26 25
N.C. 37
OPSAFE1 38
OPSAFE2 39
BUSY 40
DV_DD 41
DGND 42
CNVST 43
ALARM 44
CS/A0 45
SPI/I2C 46
N.C./A2 47
+
SCLK/SCL 48
MAX11014
MAX11015
24 PGAOUT2
23 PGAOUT1
22 FILT4
21 FILT3
20 FILT2
19 FILT1
18 GATE1
17 ACLAMP1
16 N.C.
15 GATEVSS
14 GATE2
13 ACLAMP2
1 2 3 4 5 6 7 8 9 10 11 12
TQFN
7mm x 7mm X 0.8mm
PROCESS: BiCMOS
Chip Information
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