MAX11014_08 Datasheet, PDF (27/70 Pages) Maxim Integrated Products – Automatic RF MESFET Amplifier Drain-Current Controllers

Automatic RF MESFET Amplifier
Drain-Current Controllers
S
SDA
SCL
Figure 12. Acknowledge Bits
1
2
SLAVE ADDRESS
NACK
ACK
8
9
S = START.
ACK = ACKNOWLEDGE.
NACK = NOT ACKNOWLEDGE.
S
0
1
0
1
SDA
A2
A1
A0
R/W
ACK
SCL
1
2
3
4
5
6
7
8
9
S = START.
ACK = ACKNOWLEDGE.
SLAVE ADDRESS BITS A2, A1, AND A0 CORRESPOND TO THE LOGIC STATE OF ADDRESS-SELECT INPUT PINS A2, A1, AND A0.
Figure 13. Slave Address Byte
Acknowledge and Not-Acknowledge Conditions
Data transfers are acknowledged with an acknowledge
bit or a not-acknowledge bit. Both the master and the
MAX11014/MAX11015 (slave) generate acknowledge
bits. To generate an acknowledge, the receiving device
pulls SDA low before the rising edge of the acknowl-
edge-related clock pulse (ninth pulse) and keeps it low
during the high period of the clock pulse (Figure 12).
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse and leaves SDA
high during the high period of the clock pulse. Monitor
the acknowledge bits to detect an unsuccessful data
transfer. An unsuccessful data transfer happens if a
receiving device is busy or if a system fault occurs. In
the event of an unsuccessful data transfer, the bus
master should reattempt communication at a later time.
Slave Address
The MAX11014/MAX11015 have a 7-bit I²C slave
address. The MSBs of the slave address are factory
programmed to 0101. The logic state of address inputs
A2, A1, and A0 determine the 3 LSBs of the device
address (Figure 13). Connect A2, A1, and A0 to DV_DD
for a high logic state or DGND for a low logic state.
Therefore, a maximum of eight MAX11014/MAX11015
devices can be connected on the same bus at one
time.
The MAX11014/MAX11015 continuously wait for a
START condition followed by its slave address. When
the device recognizes its slave address, it is ready to
accept or send data depending on bit 8, the R/W bit.
High-Speed Mode
At power-up, the bus timing is set for fast mode (F/S
mode, up to 400kHz I²C clock), which limits interface
speed. Switch to high-speed mode (HS mode, up to
3.4MHz I²C clock) to increase interface speed. The
interface is capable of supporting slow (up to 100kHz),
fast (up to 400kHz), and high-speed (up to 3.4MHz)
protocols. See Figure 14.
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