MAX11014_08 Datasheet, PDF (45/70 Pages) Maxim Integrated Products – Automatic RF MESFET Amplifier Drain-Current Controllers

Automatic RF MESFET Amplifier
Drain-Current Controllers
The current-sense calibration routine offers two opera-
tion modes: acquisition and tracking. In acquisition
mode, the calibration routine operates continuously
until the error is minimized to 50µV or less. In tracking
mode, the routine operates every 15ms to minimize
interference and allow the calibration routine more
averaging time. A sample-and-hold circuit prevents
switching noise on GATE_ during tracking mode. Set
the TRACK bit, D2, to 0 to run the calibration routine in
acquisition mode. Set TRACK to 1 to run the calibration
routine in tracking mode. Set TRACK to 0 for the first
calibration.
Set the DOCAL bit, D1, to 1 to run a current-sense
self-calibration routine in both channel 1 and channel 2.
At the end of the calibration routine, DOCAL is set back
to 0. Set the SELFTIME bit, D0, to 1 to perform a cur-
rent-sense calibration on a periodic basis, typically
every 15ms. Use the DOCAL bit in conjunction with the
SELFTIME bit. When a calibration routine is command-
ed by DOCAL, and SELFTIME is set to 1, the internal
timer is reset at the end of the routine and waits another
15ms before performing the next self-timed calibration.
The self-calibration routine can be commanded when
the DACs are powered down, but the results are not
accurate. For best results, run the calibration after the
DAC power-up time, t_DPUEXT.
ADCCON (Write)
Write to the ADC conversion register to convert the
ADCIN_, GATE_, internal DAC and sense voltages. The
ADC conversion register also converts the internal and
external temperature readings and sets the interface for
continuous conversion. See Table 19. Set the com-
mand byte to 62h to write to the ADC conversion regis-
ter. Bits D15–D12 are don’t-care bits. The ADCMON bit
in the hardware configuration register must be set to 1
to load ADC results into the FIFO. Set the CONCONV
bit, D11, to 1 for continuous ADC conversions.
Set the CH10 bit, D10, to 1 to convert the ADCIN2 volt-
age. Set the CH9 bit, D9, to 1 to convert the GATE2
voltage. Set the CH8 bit, D8, to 1 to convert the channel
2 DAC code. Set the CH7 bit, D7, to 1 to convert the
channel 2 sense voltage. Set the CH6 bit, D6, to 1 to
convert the channel 2 external temperature sensor
measurement. Set the CH5 bit, D5, to 1 to convert the
ADCIN1 voltage. Set the CH4 bit, D4, to 1 to convert
the GATE1 voltage. Set the CH3 bit, D3, to 1 to convert
the channel 1 DAC code. Set the CH2 bit, D2, to 1 to
convert the channel 1 sense voltage. Set the CH1 bit,
D1, to 1 to convert the channel 1 external temperature
sensor measurement. Set the CH0 bit, D0, to 1 to con-
vert the internal temperature sensor measurement.
Convert any combination of ADC channels through the
ADC conversion register. When requesting a conver-
sion of more than one channel, the channels are con-
verted in numerical order from CH0 to CH10.
Setting the CONCONV bit to 1 may cause the FIFO to
overflow if data is not read out quickly enough.
Continuous-conversion mode is only available in clock
modes 00 and 01. See the Clock Mode 00 and Clock
Mode 01 sections. The ADC does not trigger a busy
signal when the CONCONV bit is set. If a temperature
channel is included in the scan when CONCONV is set,
the internal reference and temperature sensor remain
powered up until CONCONV is set to 0. Similarly, if an
ADC measurement using the internal reference is
included in the scan, the internal reference is turned on
prior to the first conversion and remains on until
CONCONV is set to 0.
In clock modes 00 and 01, when the CONCONV bit is
set to 0 and the current scan (not just the current con-
version) is completed, the ADC goes to an idle state
awaiting the next command. The BUSY output is set
high when the CONCONV bit is set to 0 and remains
high until the current scan is completed. See the BUSY
Output section.
SHUT (Write)
Shut down all internal blocks, as well as the DACs,
ADCs, and gate-drive amplifiers individually, through
the shutdown register. See Table 20. Set the command
byte to 64h to write to the shutdown register. Bits
D15–D12 are don’t care. Set the FULLPD bit, D11, to 1
to shut down all internal blocks and reduce AV_DD sup-
ply current to 0.8µA. The FULLPD bit is set to 1 at
power-up. Set the FULLPD bit to 0 before writing any
other commands to activate all internal blocks and
functionality.
Set the FBGON bit, D10, to 1 to keep the internal
bandgap reference powered up. Set the WDGPD bit,
D9, to 1 to turn off the watchdog oscillator and prevent
self-monitoring of the watchdog timer. Set the OSCPD
bit, D8, to 1 to power down the internal oscillator. Set
the PD2-3 bit, D7, to 1 to power down the channel 2
current-sense amplifier. Set the PD2-2 bit, D6, to 1 to
power down the channel 2 gate-drive amplifier. Set the
PD2-1 bit, D5, to 1 to power down the channel 2 DAC
summing node. Set the PD2-0 bit, D4, to 1 to power
down the channel 2 DAC. Set the PD1-3 bit, D3, to 1 to
power down the channel 1 current-sense amplifier. Set
the PD1-2 bit, D2, to 1 to power down the channel 1
gate-drive amplifier. Set the PD1-1 bit, D1, to 1 to
power down the channel 1 DAC summing node. Set the
PD1-0 bit, D0, to 1 to power down the channel 1 DAC.
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