MAX11014_08 Datasheet, PDF (6/70 Pages) Maxim Integrated Products – Automatic RF MESFET Amplifier Drain-Current Controllers

Automatic RF MESFET Amplifier
Drain-Current Controllers
SPI-INTERFACE TIMING CHARACTERISTICS
(Note 9) (See Figure 1.)
PARAMETER
SCLK Clock Period
SCLK High Time
SCLK Low Time
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Fall to DOUT Transition
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Rise or Fall to SCLK Rise
CS Pulse-Width High
Last SCLK Rise to CS Rise
SYMBOL
t_CP
t_CH
t_CL
t_DS
t_DH
t_DO
t_DV
t_TR
t_CSS
t_CSW
t_CSH
CONDITIONS
C_L = 30pF
C_L = 30pF (Note 3)
C_L = 30pF (Note 10)
(Note 3)
(Note 3)
MIN
TYP
MAX
UNITS
40
ns
16
ns
16
ns
10
ns
0
ns
20
ns
40
ns
40
ns
10
ns
40
ns
0
ns
I²C-INTERFACE SLOW-/FAST-MODE TIMING CHARACTERISTICS
(Note 9) (See Figure 2.)
PARAMETER
SCL Clock Frequency
Bus Free Time Between a STOP
and START Condition
Hold Time (Repeated) for START
Condition
Setup Time for a Repeated START
Condition
SCL Pulse-Width Low
SCL Pulse-Width High
Data Setup Time
Data Hold Time
SYMBOL
f_SCL
t_BUF
CONDITIONS
t_HD;STA
After this period, the first clock
pulse is generated
t_SU;STA
t_LOW
t_HIGH
t_SU;DAT
t_HD;DAT
(Note 11)
MIN
TYP MAX
0
400
1.3
0.6
0.6
1.3
0.6
100
0
0.9
SDA, SCL Rise Time, Receiving
t_R
(Notes 3, 12)
0
300
SDA, SCL Fall Time, Receiving
SDA Fall Time, Transmitting
t_F
(Notes 3, 12)
t_F
(Notes 3, 12, 13)
0
300
20 + 0.1 x C_B
250
Setup Time for STOP Condition
t_SU;STO
0.6
Capacitive Load for Each Bus Line
C_B
(Notes 3, 14)
400
Pulse Width of Spikes Suppressed
By the Input Filter
t_SP
(Note 15)
50
UNITS
kHz
µs
µs
µs
µs
µs
ns
µs
ns
ns
ns
µs
pF
ns
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